Synopsys StarRC Parasitic Extraction Engineer Jobs: Apply
StarRC sits at the tail of the physical design flow, but its output is what decides whether timing sign-off can be trusted. A StarRC parasitic extraction engineer produces the RC parasitics that STA engineers and power teams load into PrimeTime and PrimePower at sign-off. Get the extraction wrong and every downstream timing number is wrong with it.
The daily skills are StarRC extraction setup, technology file management, and integration with PrimeTime for SPEF-based timing sign-off. You are expected to know the extraction modes, from the faster fundamental mode through the field solver, and to judge when the extra accuracy is worth the runtime. At 7nm and below that call gets harder, because multi-patterning makes extraction color-aware and the mask decomposition feeds the parasitic result alongside the tech file.
Two roles consume StarRC output directly: static timing analysis and physical design. On the tool side, StarRC and Cadence Quantus are the two extraction engines you meet in production, and a team's choice usually tracks its sign-off STA tool, PrimeTime or Tempus.
Hiring concentrates at companies that own their back-end sign-off. Apple, Nvidia, Qualcomm, AMD, Broadcom, and Intel all staff dedicated extraction and signoff engineers, and the AI accelerator startups taping out at 5nm and 3nm need the same skills, often without a deep methodology bench behind them. Foundry PDK and methodology groups hire here too, since the extraction tech files ship with the process.
If you are moving into this specialty, the thing worth doing is getting through one full tapeout owning the extraction and sign-off handoff, then being ready to talk specifics. Which corners you signed off, how you closed a stubborn coupling-related violation, what you scripted to make the flow repeatable. That reads far better in an interview than a resume line that says you have used StarRC.
Pay tracks seniority and metro more than the tool name. In the US market, senior back-end signoff engineers generally sit in the $150K to $230K total-comp band, with staff and principal levels reaching higher. The salary guide for semiconductor jobs breaks the numbers out by level and location.
Roles that ask for StarRC cluster at shops with a clear Synopsys relationship, so read a team's tool stack before you apply. Save a StarRC search on semidesignjobs.com and a matching role lands in your inbox when it posts.
FAQ
What is RC parasitic extraction, and why is StarRC central to sign-off?
RC parasitic extraction models the resistance and capacitance of the real metal interconnect in a routed layout. Those parasitics set the actual propagation delays and signal-integrity behavior of the chip. StarRC writes them out as a SPEF file, which PrimeTime reads for timing sign-off. If the parasitics are off, you get false timing closure or missed violations, so extraction quality gates everything downstream.
How does StarRC compare to Cadence Quantus?
StarRC from Synopsys and Quantus from Cadence are the two most widely used parasitic extraction tools, each living mainly inside its vendor's sign-off flow. Both write SPEF that STA and power tools consume, and their accuracy and runtime are close for most design styles. Teams usually pick based on their primary STA tool, PrimeTime for StarRC and Tempus for Quantus.
How do advanced nodes change StarRC methodology?
At 7nm and below, multi-patterning adds lithography-dependent parasitic variation, so extraction becomes color-aware. EUV mask constraints and double or triple patterning decomposition shift inter-metal coupling capacitance, which the models have to account for. StarRC handles this through advanced technology-file configurations that arrive with foundry PDK updates, so keeping the PDK current is part of the job.