Power Analysis Engineer Jobs: Find IC Power Signoff Roles
Every tapeout has a power sign-off gate before mask submission, and power analysis engineers own it. Their job is to verify that the chip's power delivery network holds up under realistic switching conditions: IR-drop, electromigration, dynamic power, and thermal margins all have to close before the design goes to the fab.
The core tools are Synopsys PrimePower for dynamic and static power estimation, Cadence Voltus for power rail analysis and IR-drop sign-off, and Ansys RedHawk-SC for full-chip power grid integrity at advanced nodes. Most teams run at least two of these in their sign-off flow; proficiency in one is typically a baseline requirement.
A typical project cycle involves extracting toggle rates from simulation, running dynamic power analysis in PrimePower, then handing current maps to the Voltus or RedHawk flow for IR-drop sign-off. At each step the engineer is reconciling what the design intends to do with what the power grid can actually support.
At 5nm and below, power integrity gets harder. Smaller via stacks, tighter margins, and higher current densities mean that floorplan decisions upstream have a direct impact on whether power sign-off closes. Power analysis engineers regularly feed constraints back to the physical design team during floorplanning to set power grid geometry early, before the layout hardens.
Low-power design engineers work the RTL and architecture side of the same problem: clock gating, power domains, and voltage islands. Power analysis engineers verify the implementation after synthesis and layout; the two roles are complementary and routinely collaborate on UPF/CPF sign-off.
Companies hiring for these roles include Qualcomm and Apple for mobile SoC work, Nvidia and AMD for data center and GPU chips, and a growing number of AI chip startups where the thermal and power envelope is a first-class design constraint. The work is back-end focused but requires enough understanding of RTL and architecture to trace power issues back to their source.
Mid-level power analysis engineers earn roughly $150K-$210K in total compensation. Senior and staff roles at Nvidia or Apple push higher. The semiconductor salary guide has current range data broken down by role level and geography.
Save a search on semidesignjobs.com and you'll get an email when a matching power analysis engineer role opens. Filter by node, tool stack, or company type to keep the signal tight.
FAQ
What tools are most important for power analysis engineer jobs?
Synopsys PrimePower and Cadence Voltus are the leading power sign-off tools. Ansys RedHawk-SC is widely used for full-chip power integrity analysis at advanced nodes. Proficiency in at least one of these platforms is typically required; teams running both Voltus and RedHawk in parallel for cross-validation are common at larger companies.
How is IR-drop analysis performed in power analysis engineer roles?
IR-drop analysis simulates resistive voltage drop in the chip's power delivery network under realistic switching conditions. Engineers extract power grid netlists, apply current maps from switching activity data, and use Voltus or RedHawk to identify cells operating below the minimum supply voltage. Static and dynamic IR-drop are both checked; dynamic is typically the binding constraint at advanced nodes.
What is the relationship between power analysis and low-power design?
Low-power design engineers reduce power consumption at RTL and architecture level through clock gating, power domains, and multi-voltage techniques. Power analysis engineers perform back-end sign-off to verify that the implemented design meets power and IR-drop specifications. The two roles share UPF/CPF ownership and typically collaborate closely during sign-off iterations.