Floorplan Engineer Semiconductor Jobs: Browse Open Roles
Floorplanning sits at the start of the physical implementation flow, and decisions made here propagate all the way to tapeout. A poor macro placement, an undersized power ring, or a misaligned clock trunk can make timing closure impossible downstream, regardless of how much effort goes into place and route afterward.
Floorplan engineers work inside Cadence Innovus or Synopsys ICC2 to partition the die, place hard macros and memory arrays, define I/O pad rings, and establish the power delivery network topology. They set voltage area boundaries, stub out the global clock trunk, and run early timing estimates to validate that the partition will close before standard cell placement begins. Reading both the netlist and the physical intent simultaneously is a baseline skill.
Coordination with architects and RTL designers is constant. Architects provide timing and area budgets; floorplan engineers translate those into a spatial arrangement the router can work with. The deliverable is a constraints file and an initial DEF that the place and route team picks up downstream. Problems caught at floorplan stage are far cheaper to fix than problems surfaced during sign-off; that leverage is why experienced engineers are valued here.
At advanced nodes (5nm, 3nm), floorplan quality has an outsized effect on schedule. A floorplan that constrains routing too tightly can add weeks of iteration in place and route. Companies working at leading nodes often staff senior floorplan engineers well before P&R begins to get the constraints right early.
This role sits within the broader physical design discipline, but floorplan-focused engineers spend less time on detailed cell-level implementation and more time on die-level strategy and constraint authoring. On large SoC programs, floorplan may be a standalone job family; on smaller teams, the same engineer covers both.
Companies actively posting floorplan engineer roles include Qualcomm, Broadcom, and Nvidia, along with automotive and networking chip teams building mixed-signal SoCs. AI chip startups also hire for these roles, particularly at 5nm and 3nm where the stakes of an early floorplan decision are highest.
Compensation for experienced floorplan engineers typically runs $160K-$220K in total comp, with senior roles at hyperscaler in-house silicon teams at the higher end. See the semiconductor salary guide for current range data by role level.
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FAQ
Why is floorplanning so critical in semiconductor physical design?
Floorplanning decisions set the physical constraints for all downstream implementation steps. A poor floorplan can make timing closure impossible no matter how good the place-and-route effort is. Early floorplan quality directly impacts schedule, power delivery network sizing, and final chip area - and rework is expensive once downstream steps have built on top of those decisions.
What does a floorplan engineer do on a typical workday?
A typical day involves running floorplan experiments in Innovus or ICC2, analyzing timing and congestion estimates, attending design reviews with the front-end team, and refining macro placement based on physical synthesis feedback. Iterating on power grid topology and voltage area definitions is also common, especially during the early stages of a new design.
How is floorplan engineering different from place and route?
Floorplanning is the early-stage process of defining block and macro locations, I/O placement, and power grid structure. Place and route is the detailed automated process that follows, placing standard cells and routing all signal wires within the floorplan constraints. Floorplan quality determines the upper bound on what place and route can achieve.