Low Power Design Engineer Positions: Browse IC Power Roles

Power budget stopped being a post-layout problem when mobile SoC teams realized that architecture decisions at RTL determine most of the outcome. Low power design engineers own those decisions from the first architecture review through tapeout signoff.

At the RTL level, the core techniques are clock gating with ICG cells, operand isolation to suppress spurious switching on idle datapaths, and careful reset synchronization. These choices compound across a design: architecture-level power decisions are difficult to recover in physical implementation, which is why low power engineers get involved early in the project, not at the end.

Above RTL, engineers define and maintain multi-voltage domain implementations using UPF (IEEE 1801) or CPF. UPF specifies power domains, supply voltages, isolation rules, and retention policies, flowing through simulation, synthesis, and physical implementation as the authoritative power intent. For a technical grounding in the methodology, see the post on low power ASIC design and UPF/IEEE 1801.

Apple, Qualcomm, MediaTek, and Samsung post consistent volume of low power design roles for their mobile SoC and application processor teams. IoT chip startups targeting fitness trackers, hearing aids, and industrial sensors have pushed requirements further, demanding always-on sensor blocks with standby power in the nanowatt range. Power analysis engineer jobs cover the signoff side of this work, where engineers run Synopsys PrimePower or Cadence Joules against activity data to validate the power budget before tapeout. Synthesis engineer ASIC positions overlap where low-power techniques like multi-threshold cell libraries and scan power optimization get applied in the flow.

Base compensation for low power engineers with demonstrated UPF methodology at leading-edge nodes runs above median ASIC design rates. The semiconductor salary guide tracks current ranges by seniority and region.

Save a search on semidesignjobs.com filtered to "UPF" or "low power" and you'll get an email when new positions open. Both mobile-tier and data-center power roles are active in the current cycle.

FAQ

What is UPF and why is it important for low power design engineer positions?

UPF (Unified Power Format, IEEE 1801) is the standard language for describing power intent: power domains, supply voltages, isolation rules, and retention policies. Low power design engineers develop and maintain UPF files consumed by simulation, synthesis, and physical implementation tools throughout the design flow.

What RTL coding practices support low power design?

Clock gating with ICG cells, operand isolation to suppress spurious switching on idle datapaths, and careful reset synchronization are the primary RTL-level techniques. Minimizing toggle rates through architectural choices also contributes substantially to power reduction, before any physical optimization is applied.

How has the growth of wearables and IoT impacted low power design engineer positions?

Wearable and IoT devices demand always-on sensors and ultra-low standby power, pushing low power design to the foreground of chip requirements. The market now extends beyond mobile into fitness trackers, hearing aids, implantables, and industrial sensors, each with its own nanowatt-level power budget.