PDN Design Engineer Jobs: Find Power Network Design Roles
Every transistor on a chip needs clean, stable power, and the engineers who make that happen are hard to find. PDN design touches physical design, packaging, and signoff all at once, and hiring pressure has only increased as power budgets balloon at 5nm and below.
The work centers on designing the hierarchical metal stack that routes VDD, GND, and multiple power domain rails from flip-chip bumps down through the chip's metal layers. You plan the metal layer stack-up, assign C4 bumps for power and ground, and co-simulate the die-side network with the package substrate team to minimize end-to-end impedance. At 5nm and 3nm, even small mistakes in bump placement or stripe density show up as IR-drop violations that kill frequency targets.
On the tool side, Cadence Voltus handles static and dynamic IR-drop analysis, Ansys RedHawk-SC does chip-package co-simulation, and Synopsys Galaxy covers power integrity signoff. If you have used any of these in a tapeout flow, you know the loop: run analysis, find hotspots, widen stripes or add decap, re-run. PDN work overlaps with power integrity engineering, which leans more toward analysis and signoff, while physical design roles cover the broader implementation context.
Apple, Nvidia, AMD, Qualcomm, and the hyperscaler silicon teams at Google, Amazon, and Microsoft all hire for this. AI accelerator startups need PDN engineers too, because their chips run at high sustained power with aggressive clock gating transients that stress every rail. Those transients are shaped by the clock tree synthesis choices made upstream. Mid-career PDN engineers in the US typically see $140K to $190K base, with staff-level total comp past $250K at larger firms. The salary guide has broader compensation numbers.
Set up a search on semidesignjobs.com filtered to physical design or power-related roles and you will get notified when new PDN design engineer positions are posted.
FAQ
What is a power delivery network in IC design
A power delivery network is the hierarchical system of metal rails, vias, C4 bumps, and package traces that distributes power from the voltage regulator to every active circuit on the chip. A robust PDN minimizes IR-drop and ensures reliable circuit operation across all switching activity scenarios.
How does flip-chip packaging affect PDN design
Flip-chip packaging distributes C4 bumps across the entire die surface, enabling much lower supply inductance and resistance compared to wire-bonded packages. PDN design engineers co-optimize bump placement, die-side PDN density, and package routing with substrate designers to achieve minimum impedance from regulator to silicon.
What is the difference between static and dynamic IR-drop analysis
Static IR-drop analysis calculates voltage drop under worst-case average current conditions, providing a conservative bound. Dynamic IR-drop analysis simulates transient current surges from simultaneous switching activity, capturing instantaneous voltage droops that static analysis may miss. Most signoff flows require both.