Floor Planning Physical Design Jobs: Find Block Layout Roles
Floor planning sits at the boundary between architecture and physical implementation. The engineer who owns the floorplan decides how a multi-billion-gate SoC gets partitioned across the die, where power grids fan out, and how top-level signal routing connects major functional blocks. Get it wrong early and you pay for it in every downstream PnR iteration.
The core toolchain is Cadence Innovus or Synopsys ICC2 for hierarchical floorplanning, with physical synthesis (DC-Topo, Genus iSpatial) used to generate early area, timing, and congestion estimates before full place-and-route runs are available. Engineers also need to understand package I/O constraints: bump grid rules, ball assignment, and wire bond geometry all dictate where I/O cells land on the die edge.
Floor planning engineers who also own power planning, metal layer allocation, bump assignment, and power via placement, tend to get pulled into every major SoC program. The role overlaps with pure floorplan engineer positions, and place-and-route roles pick up where the floorplan hands off.
Apple, Nvidia, Qualcomm, AMD, Intel, and Marvell all run SoCs large enough to need dedicated floorplan owners. AI accelerator startups and hyperscaler in-house teams are staffing up too as their designs get bigger. US base salaries sit in the $140K to $180K range for mid-career engineers, with total comp at staff level clearing $250K or more at the tier-one companies. The salary guide has current numbers by region.
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FAQ
How does hierarchical floorplanning work in large SoC designs
The chip gets divided into independently implemented blocks, each with defined budgets for area, timing, and pin placement. Block teams implement their partitions separately, then the top-level team assembles them and manages inter-block routing and integration timing. This approach scales to designs with hundreds of millions of cells.
What physical synthesis techniques are used in early floorplan exploration
Physical synthesis tools like DC-Topo and Genus iSpatial apply placement awareness during synthesis to produce netlists optimized for a target floorplan. Engineers use the results to generate early estimates of block timing, area, and congestion that inform partition decisions before full PnR runs are available.
How do package constraints affect floor planning physical design jobs
Package constraints, including bump grid, ball grid, and wire bond rules, dictate where I/O cells and ESD devices must sit on the die. Floorplan engineers route high-speed I/O signals like DDR and SerDes to the die edge with minimal detours while meeting all signal integrity requirements.