Mid-Level Analog Layout Engineer Jobs: Browse Custom IC Roles
The jump from junior to mid-level analog layout is the point where the circuit designer stops sitting next to you. With 3 to 7 years of custom transistor-level work behind you, a mid-level req expects you to run the full layout cycle on a moderately complex block yourself: transistor placement, analog-critical routing, DRC and LVS clean, and post-layout simulation sign-off.
The general category sits under analog layout engineer jobs; the mid-level slice is defined by independence rather than tool count.
What that independence looks like in practice: you set your own floorplan strategy, apply device matching from the schematic without per-device direction, and work through DRC and LVS violations as they show up instead of saving them for a frantic pass at the end. You know that a long route on a sensitive node is a problem before the parasitic extraction tells you so.
Who hires for it: fabless companies building mixed-signal SoCs, dedicated analog IP houses, and power management and data-converter teams where layout quality shows up directly in silicon performance. Precision matching on a current mirror is not a checkbox at these shops; it is the difference between a part that meets spec and one that does not.
Mid-level analog layout engineers at leading fabless companies and analog IP companies typically earn $140K to $195K in total compensation, with the high end concentrated in California and the data-converter and RF segments. The salary guide for semiconductor jobs has the fuller breakdown by level and region.
If you are mapping where layout skills carry into neighboring silicon roles, entry-level ASIC design engineer jobs is a useful contrast point. Save a search on semidesignjobs.com and you will get an email when a mid-level analog layout role matching your filters opens.
FAQ
What matching techniques are expected at the mid-level analog layout engineer level
Common-centroid layouts for differential pairs and current mirrors, interdigitated transistor arrays to cut mismatch, and guard rings for isolation. A mid-level layout engineer applies these from the schematic and the design guidelines independently, without the circuit designer walking through each device.
How does the DRC/LVS closure process work in mid-level analog layout engineer jobs
You run DRC and LVS in Siemens Calibre or Synopsys ICV iteratively as layout develops, fixing violations as they appear rather than batching them. LVS mismatches get resolved by comparing the extracted netlist against the source schematic to find the missing connection or the short.
What is post-layout simulation and why does it matter in analog layout
Post-layout simulation extracts parasitic resistance and capacitance from the finished layout with tools like Cadence Quantus or Synopsys StarRC, then reruns the circuit with those parasitics in. It confirms that routing, especially on sensitive analog nodes, has not pushed the block below spec before the layout is called final.