Chiplet Design Engineer Jobs: Find 2.5D and 3D-IC Roles
AMD's EPYC and MI300 series, Intel's Ponte Vecchio, and a growing list of AI chip startups have turned chiplet integration from a research project into a production engineering discipline. Chiplet design engineer roles have grown alongside it.
The work sits at the intersection of IC design and advanced packaging. Engineers handle die-to-die interface design using UCIe, HBM, AIB, or proprietary protocols; interposer layout for 2.5D integration; micro-bump floor planning and routing; power delivery analysis across the multi-die stack; and the co-design constraints that flow between chip die, interposer, and package substrate. Thermal analysis of closely tiled or stacked dies is a recurring challenge with no equivalent in monolithic ASIC work.
UCIe (Universal Chiplet Interconnect Express) has become the open standard for die-to-die connectivity, backed by AMD, Intel, Qualcomm, Arm, and TSMC. Engineers who can design and verify UCIe PHY and protocol layers are scarce relative to the current level of demand.
Physical design engineers moving into chiplet roles add packaging awareness to existing floorplan and placement skills: constraining bump arrays, managing keep-outs for bonding structures, and co-simulating the die alongside the package. Power integrity engineers are equally important on chiplet teams; switching transients across die-to-die interfaces can be severe, and PDN co-design across die and package is more complex than in a single-die SoC.
Chiplet programs also require coordination between IP teams, packaging engineers, and OSAT partners in ways that monolithic ASIC projects do not. Engineers who can translate chip-level constraints into package-level requirements across these groups are the hardest positions to fill.
AMD builds chiplet teams across its EPYC, Radeon, and Versal product lines in Santa Clara and Austin. Intel runs Foveros (3D stacking) and EMIB (2.5D embedded bridge) programs in Hillsboro and Santa Clara. AI accelerator startups working at the 5nm and 3nm nodes are hiring from AMD and Intel alums to build their first chiplet programs from scratch.
Base salaries run $160K–$220K at public semiconductor companies; see the semiconductor salary guide for current figures by company type and geography. AI chip startups typically offer higher base with equity upside. Staff-level engineers at hyperscaler in-house silicon teams can reach $280K+ total comp.
Search "chiplet" or "UCIe" on semidesignjobs.com to filter to the most relevant openings. Set a salary alert to track how compensation evolves as this specialty matures.
FAQ
What is UCIe and why is it important for chiplet design?
UCIe (Universal Chiplet Interconnect Express) is an open industry standard for die-to-die connectivity in chiplet-based designs. It defines the physical layer, protocol, and software stack for connecting chiplets from different vendors or processes, enabling an open chiplet ecosystem similar to how PCIe enabled platform expansion.
What are the primary design challenges in chiplet integration?
Key challenges include managing signal integrity and power delivery across die-to-die interfaces, thermal management of closely stacked or tiled dies, meeting inter-die latency requirements, and achieving reliable manufacturing yield across all dies in the package.
How is chiplet design different from standard ASIC physical design?
Chiplet design adds co-design constraints across die, interposer, and package. Physical design decisions on the chip die must account for micro-bump pitch, interposer routing resources, and package-level power delivery in ways that monolithic ASIC physical design does not require.