CXL Design Engineer Jobs: Find Cache Coherent Link Roles
CXL design engineers build the protocol stack that makes Compute Express Link functional in production silicon: the cache-coherent interconnect now being deployed in data center platforms to attach memory expanders, AI accelerators, and computational storage to host CPUs.
The technical scope breaks into three sub-protocols. CXL.io handles non-coherent I/O traffic. CXL.cache enables device-to-host coherency. CXL.mem gives the host managed access to device memory. CXL 2.0 added switching and memory pooling; CXL 3.0 extended that to fabric topologies with multi-level memory sharing. Day-to-day work involves controller RTL design, UVM testbench development against compliance test suites, and PHY integration with PCIe Gen 5 or Gen 6 physical layers. Background in PCIe design transfers directly, since CXL shares that electrical interface.
Protocol verification is where the complexity concentrates. Multi-master coherency state machines, memory ordering requirements, and device class-specific transaction flows all need systematic coverage. CXL VIP from Synopsys or Cadence provides the compliance test suite foundation; engineers who build additional UVM agents for micro-architectural edge cases on top of that VIP are particularly valuable during tapeout cycles.
Intel, Samsung, SK Hynix, Micron, and Marvell each have active CXL product lines. AI chip startups building inference accelerators are also investing in CXL attach for memory bandwidth expansion, and engineers who have contributed at both specification and RTL implementation levels tend to have the most leverage in those conversations. DDR memory controller roles sit adjacent on the memory interface spectrum, relevant for engineers whose interest leans toward bandwidth-critical controller design rather than cache coherency protocols specifically.
Senior CXL positions at established companies typically range from $180K to $260K total compensation. Startups in the memory expansion space generally add meaningful equity on top of that.
Set up a filtered search on semidesignjobs.com with "CXL" or "cache coherent interconnect" and you'll receive an alert when new roles post.
FAQ
What is CXL and how does it differ from PCIe?
CXL (Compute Express Link) is a cache-coherent interconnect protocol built on the PCIe physical layer. Where PCIe handles non-coherent I/O, CXL adds CXL.cache and CXL.mem sub-protocols that enable shared coherent memory access between hosts and accelerators, which PCIe alone cannot provide.
What devices use CXL interfaces in data center applications?
Memory expanders, smart NICs, GPUs and AI accelerators, persistent memory devices, and computational storage drives. Intel, Samsung, SK Hynix, Micron, and Marvell are active in CXL product development; several AI chip startups are building CXL-attached memory devices as well.
How complex is CXL protocol verification compared to PCIe?
Substantially more complex. Cache coherency protocols introduce multi-master state machines, memory ordering requirements, and device class-specific transaction flows that PCIe verification does not have. Specialized CXL VIP from Synopsys or Cadence is standard for compliance testing, but thorough verification requires additional stimulus beyond what the VIP suite exercises.