Alphawave Semiconductor SerDes Design Engineer Jobs
Alphawave Semi sells one thing: ultra-high-speed wireline connectivity IP. That means SerDes PHYs, PCIe and CXL controllers, Ethernet, and UCIe die-to-die interconnects. If you design 112G or 224G PAM4 links for a living, this is a company built around exactly that work.
The SerDes design engineer roles here split across analog front-end design, digital equalizer development, and full-custom circuit implementation at advanced nodes. On the analog side you will work on CTLE, DFE, and PLL circuits. Full-custom layout experience at 7nm, 5nm, or 3nm matters, and PAM4 signaling plus 112G-and-up SerDes experience moves a resume to the top of the stack.
Digital roles focus on the equalization and adaptation logic that keeps a 224G link open across a lossy channel, plus the calibration firmware that trims the analog front end at startup. Mixed-signal engineers sit between the two, closing timing and noise budgets that neither side owns alone.
The company ships multi-generational product families running from 28G up to 224G PAM4, often ahead of the standards bodies. Roadmaps here move on IP-vendor time, not product-cycle time, so a design engineer may touch two or three PHY generations in the span one chip company would spend on a single SoC. That pace is both the appeal and the pressure.
SemiDesignJobs lists Alphawave openings from Toronto (HQ), San Jose, Austin, Munich, and Bengaluru. Filter by interface standard, discipline (analog, digital, or mixed-signal), and location. A lot of the current demand traces to hyperscalers buying 112G and 224G SerDes IP for their AI accelerators, which puts Alphawave squarely in the AI chip supply chain, near frontier chipmakers like Cerebras. For a wider view of who else is hiring, see our roundup of companies hiring for semiconductor design jobs.
Alphawave was founded in 2017 by former Rambus engineers and trades on the London Stock Exchange under AWE. It later acquired OpenFive to add custom ASIC design services, so some roles reach into full-chip work rather than IP alone. Pay for 112G-and-up SerDes specialists sits near the top of the analog and mixed-signal IC range, reflecting how few engineers can do it well.
If high-speed wireline is your niche, save a search on semidesignjobs.com and you will get an email when a matching Alphawave role opens. For adjacent openings, look at Rambus interface IP engineer jobs and broader SerDes design engineer jobs.
FAQ
What SerDes speeds does Alphawave design IP for?
Alphawave's SerDes IP spans 25G to 224G per lane, covering PCIe Gen 6, CXL 3.0, 800GbE and 1.6TbE Ethernet, and UCIe die-to-die links. Next-generation 224G PAM4 and 448G PAM4 work is in progress.
What process nodes does Alphawave use for its SerDes IP?
Alphawave implements SerDes PHY on leading-edge TSMC 3nm, 5nm, and 7nm, plus Samsung Foundry nodes. Full-custom circuit skill at these nodes is a core requirement for its SerDes design engineers.
Is Alphawave a publicly traded company?
Yes. Alphawave Semi trades on the London Stock Exchange under the ticker AWE. It was founded in 2017 and has grown through in-house development and acquisitions, including OpenFive for custom ASIC design services.