Rambus Interface IP Design Engineer Jobs
Rambus started as an RDRAM memory-interface company and turned into one of the few IP houses whose PHYs end up inside other companies' flagship chips. Design interface IP at Rambus and your DDR5 or PCIe Gen 6 block can be licensed into dozens of SoCs rather than shipping in a single product. That reach is what pulls a lot of engineers in.
Rambus interface IP design engineer jobs center on high-speed PHY work: DDR5 and LPDDR5 PHY design, PCIe Gen 5 and Gen 6 controllers and PHYs, HBM2E and HBM3 interfaces, and GDDR7 development. The roles ask for real depth in mixed-signal SerDes, PHY circuit design, and equalization, plus enough DRAM and PCIe protocol knowledge to close timing against a spec that may not be final yet.
That last part is the interesting bit. Rambus engineers often build PCIe Gen 6, CXL 3.0, DDR6, and HBM4 PHY IP before the standards lock, working next to JEDEC, PCI-SIG, and the MIPI Alliance. The same instinct for shipping ahead of the spec shows up at Alphawave Semi SerDes design engineer jobs, a company former Rambus engineers founded. Signal integrity analysis at these data rates is a first-class skill, not an afterthought, and advanced-node experience separates candidates fast.
The work maps straight onto data center demand. AI training clusters keep raising the memory-bandwidth bar, and the PHYs feeding GPUs and accelerators are what keep those pipelines full. Engineers who have tuned a SerDes design link or debugged a DDR memory controller at speed will recognize the problems here.
Rambus runs interface IP teams from its San Jose, CA headquarters, plus Sunnyvale, CA, Austin, TX, Ottawa, Bangalore, and Seoul. Titles range across circuit design, architecture, and verification, so the same filters that surface a PHY circuit role will also surface the verification and modeling positions that support it.
Compensation for high-speed IP roles tracks the broader mixed-signal market, which stays strong for engineers who can show tapeout-proven PHY work at advanced nodes. There are not many people who can design a clean multi-gigabit link, and that scarcity keeps senior and staff roles competitive.
Related openings sit under Rambus security IP engineer jobs and DDR PHY design engineer jobs. Register on semidesignjobs.com, set an alert, and a Rambus opening that matches your filters will land in your inbox.
FAQ
What memory and interface standards does Rambus design IP for?
Rambus IP covers DDR5, LPDDR5, DDR4, PCIe Gen 5 and Gen 6, HBM2E and HBM3, GDDR6 and GDDR7, and CXL 2.0. The company also provides security IP including root-of-trust and anti-counterfeiting cores.
What skills are most important for Rambus interface IP design roles?
Strong mixed-signal IC design, high-speed PHY and SerDes architecture, and familiarity with DDR or PCIe protocol specifications are the core requirements. Signal integrity analysis and advanced process node experience are the main differentiators.
Does Rambus license or sell silicon?
Rambus mainly licenses IP to chip companies, but it also designs and sells silicon products including DDR memory buffer chips and security modules. IP design engineers work closely with licensees to get the integration right.