Cerebras AI Chip Design Engineer Jobs
Cerebras builds one chip where everyone else builds hundreds. The Wafer-Scale Engine 3 puts 900,000 AI cores on a single 46,225 mm² die, roughly 57 times the area of a standard GPU die. Cerebras AI chip design engineer jobs exist because that form factor breaks most of the assumptions behind a conventional flow.
The work centers on wafer-scale integration. That means on-chip interconnect tying 900,000 cores together, high-density SRAM arrays, AI core microarchitecture, and physical design at a scale no foundry flow was built for. Power delivery has to feed roughly 23 kilowatts across the wafer. Thermal gradients run the full width of the die. Clock distribution has to stay coherent at gigahertz speeds from one edge of the wafer to the other. Defect tolerance is a design constraint from day one, not a yield problem you patch later, because you cannot scrap a whole wafer over a handful of bad cores.
Most roles want strong digital VLSI design, wafer-scale physical design experience, and real time with high-density SRAM. Knowing how AI training workloads behave helps when you make architectural tradeoffs, since the whole point of the WSE is keeping large language model training resident in on-wafer memory and bandwidth instead of shuttling it off-chip.
Cerebras runs a concentrated engineering team out of Sunnyvale, CA rather than a web of distributed design centers, so Sunnyvale is where nearly all of this happens. The team stays small relative to the size of the problem, which is why most openings target senior engineers who can own a block end to end.
If wafer-scale integration is the kind of problem you want to spend a few years on, these are among the few seats in the industry where you can. Cerebras openings sit alongside work at Tenstorrent and other AI chip design engineer jobs on the board. Save a search on SemiDesignJobs and you will get an email when a matching Cerebras role opens.
FAQ
What makes Cerebras AI chip design engineering unique
The WSE is a wafer-scale device with more than 4 trillion transistors on a single 46,225 mm² die. That creates problems around wafer-level power delivery, cooling, defect tolerance, and on-chip communication that simply do not come up in conventional reticle-sized chip design.
What experience level does Cerebras hire for these roles
Mostly senior and above. Wafer-scale design is hard and the team is small, so openings usually want 5+ years of digital VLSI or physical design work, ideally with some AI chip exposure. Exceptional candidates below that bar occasionally get through, but they are the exception.
Where is Cerebras Systems located
The headquarters and primary engineering team are in Sunnyvale, CA. Cerebras does not run large satellite design centers, so Sunnyvale is effectively the hub for all of its chip design work.