Zebu Flow Engineer
Join SiFive's System Validation team to develop and maintain build and debug flows for modeling RISC‑V CPUs on emulation platforms (primarily Synopsys ZeBu) and FPGA-based platforms. The role focuses on integrating emulator flows into the internal wake-based build system, debugging hardware/software interactions, and automating runtime and debug workflows.
Entry-level — requires at least 1 year of relevant industry experience.
Primary responsibilities include building and sustaining emulator and FPGA flows, debugging failures across hardware and software, and automating debug/runtime tooling.
Must-have technical skills and attributes.
Bachelor's or Master’s degree in Computer Science or Electronics and Communication Engineering is required. The posting specifies a minimum of 1+ years of relevant experience. No certifications or "equivalent experience" language was provided.
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
