Zebu Flow Engineer

Job Title

Zebu Flow Engineer

Role Summary

Join SiFive's System Validation team to develop and maintain the build and debug flow for modeling RISC-V CPUs on Synopsys ZeBu and FPGA platforms. The role focuses on integrating emulator and FPGA build steps into the internal wake-based build environment and improving runtime automation and debug workflows.

Work closely with software and validation teams to diagnose hardware/software failures, automate debug procedures, and validate designs.

Experience Level

Entry-level — requires at least 1 year of relevant experience.

Responsibilities

Primary responsibilities include maintaining build flows, debugging, and automation:

• Design, implement, and maintain a modular build flow for Synopsys ZeBu models within SiFive's internal build system and transition compilation steps into the wake-based build environment.
• Port designs and flows to FPGA-based platforms and support FPGA-based validation setups.
• Perform root-cause and failure analysis across RISC-V CPU hardware and software components.
• Use emulator and FPGA debug features (waveform dumps, ILA, JTAG) to troubleshoot and validate designs.
• Formulate and test failure hypotheses via systematic elimination of possible causes.
• Develop and maintain Python and Bash scripts to automate debug workflows and integrate ZeBu runtime automation with SiFive's manager ecosystem.
• Collaborate cross-functionally with software and validation engineering teams.

Requirements

Must-have technical skills and behaviors:

• Strong understanding of digital logic design.
• Experience with Verilog and porting designs onto FPGA platforms.
• Practical experience with Linux and scripting in Python and Bash.
• Experience writing automation or debug scripts and integrating tools into engineering workflows.
• Proactive, continuous learner with a collaborative approach and attention to detail.

Nice-to-have:

• Experience with hardware emulators such as Synopsys ZeBu or similar FPGA emulation platforms.
• Familiarity with JTAG, ILA, and waveform-based debugging tools.

Education Requirements

Bachelor’s or Master’s degree in Computer Science or Electronics and Communication Engineering is required. Position requires a minimum of 1+ years of relevant experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.