ZeBu Backend Floorplanning Intern
Internship on the ZeBu backend team focused on floorplanning and FPGA compilation for emulation designs. The intern will work with mentors and backend engineers to develop reproducible testplans, perform floorplanning on extracted benchmarks, and evaluate the impact on compilation performance.
This is an in-office, full-time 8-week internship based in Hsinchu, Taiwan, starting in July 2026.
Entry-level (Internship)
Under mentor supervision, contribute to floorplanning and backend evaluation for ZeBu emulation designs and help automate associated workflows.
Core skills and experience required for productive contribution during the internship.
Currently pursuing a Bachelor's or Master's degree (BSc/BS, MSc/MS) in Computer Science, Electrical Engineering, Electronic Engineering, Computer Engineering, Artificial Intelligence, Machine Learning, or a related technical field.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
