XPU Architect

Job Title

XPU Architect

Role Summary

Owner of the XPU compute engine architecture for the A-0 and A-1 systems. Initially the role will integrate and adapt third‑party IP to meet system bandwidth and memory-interface requirements, and will evolve to lead semi‑custom and custom XPU designs in future generations.

Experience Level

Senior architect level. The posting does not state explicit years of experience; candidates are expected to have substantial ASIC/architecture experience consistent with senior technical leadership (typically 7+ years).

Responsibilities

Design and deliver the compute XPU architecture focusing on performance, bandwidth, latency, and implementation feasibility.

• Define and own microarchitecture and system‑level architecture for the XPU compute engine (A‑0 and A‑1).
• Integrate and adapt third‑party IP to meet bandwidth and memory interface requirements.
• Identify and resolve system‑level bottlenecks (interconnect, memory capacity, bandwidth, latency) for inference workloads.
• Drive tradeoff analyses across performance, power, area, and cost; produce architecture specifications and implementation constraints.
• Collaborate with RTL, physical design, verification, memory and systems teams to ensure architecture is implementable and optimized for silicon constraints.
• Lead architecture evolution toward semi‑custom and fully custom compute XPU designs for future products.

Requirements

Core technical qualifications and preferred experiences.

• Must-have: Experience architecting and owning a high‑performance, high‑TDP ASIC (AI chips, network switch ASICs, high‑performance CPUs, or similar).
• Must-have: Strong knowledge of computer architecture and practical silicon implementation constraints that affect architectural options.
• Must-have: Deep understanding of AI workloads, particularly low‑latency LLM inference and its system demands.
• Must-have: Proven ability to analyze workload and system‑level bottlenecks related to interconnect, memory capacity, bandwidth, and latency.
• Nice-to-have: Hands‑on experience with AI chip architecture and tapeouts; end‑to‑end ownership of an AI ASIC project.
• Nice-to-have: Experience with HBM‑based AI chip architectures.
• Nice-to-have: Track record of product delivery and proposing unconventional or innovative chip architectures.

Education Requirements

Not specified.

About the Company

Company: Volantis Semiconductor

Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.