Workload / Performance Model Lead

Job Title

Workload / Performance Model Lead

Role Summary

Lead benchmarking and performance-infrastructure development to evaluate CPU and accelerator performance. Manage a performance team that builds benchmarks, simulators/emulators, tooling, and projection methodologies to inform architecture and software decisions.

Experience Level

Senior — requires 10+ years of industry experience in performance simulation tools and at least 5 years participating in engineering teams that deliver hardware or software products.

Responsibilities

Primary responsibilities include designing and executing benchmarks, identifying bottlenecks, and delivering tools and methodologies for performance evaluation and projection.

• Identify, develop or port, and set up benchmarks to evaluate processor and accelerator performance.
• Analyze performance bottlenecks across micro-architecture and the software stack.
• Characterize workloads on simulators, emulators, and hardware platforms.
• Develop performance-projection methodologies for complex workloads.
• Develop, deploy, and maintain tools and infrastructure for performance evaluation.
• Guide and mentor the performance engineering team and coordinate with architecture, hardware, and software teams.

Requirements

Must-have technical skills and experience, followed by concise desirable skills.

• Must-have: 10+ years direct industry experience with performance simulation tools spanning ISA to SoC/system simulators, analytical to cycle-based models, and bare-metal to virtualized environments.
• Must-have: 5+ years participating in engineering teams delivering hardware or software products.
• Must-have: Strong foundation in computer architecture for high-performance out-of-order CPU designs and workload characterization.
• Must-have: Experience with workload-reduction techniques for efficient simulation and projection.
• Must-have: Competency in discrete event simulation (DES) modeling techniques and best practices.
• Must-have: Strong software engineering practices for maintaining and refactoring large object-oriented code bases; solid OOP skills.
• Must-have: Ability to independently analyze performance bottlenecks in micro-architecture and software; awareness of security implications is a plus.
• Nice-to-have: Hands-on expertise with hardware development (RTL/implementation/verification/backend/FPGA flows) or software development (C/assembly, OS/RTOS, compilers, debuggers).
• Nice-to-have: FPGA debug experience, including Integrated Logic Analyzer (ILA) usage for waveform capture.
• Nice-to-have: Familiarity with git branching and forking workflows.

Education Requirements

MS or PhD in Computer Science or Computer Architecture (as stated in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.