Wireless R&D IP Verification Engineer, Senior Staff

Job Title

Wireless R&D IP Verification Engineer, Senior Staff

Role Summary

Lead IP-level design verification for wireless-related IP blocks. Own verification strategy, drive development of SystemVerilog/UVM environments and methodologies, and ensure coverage-driven verification and quality closure across IP/block/subsystem verification efforts.

Collaborate with global design and architecture teams, mentor junior engineers, and promote adoption of advanced DV methods (formal, emulation, gate-level) to meet project milestones and quality targets.

Experience Level

Senior — position targets experienced engineers. The posting lists overall experience guidance of 12–18 years. Degree-dependent minimums in the source: Bachelor's +8 years, Master's +7 years, PhD +6 years.

Responsibilities

Primary responsibilities focus on technical leadership of verification efforts, execution of DV tasks, cross-team collaboration, and mentorship.

• Define and own verification strategy for IP/block/subsystem verification.
• Guide development and maintenance of robust SV/UVM verification environments and methodologies.
• Ensure coverage-driven and assertion-based verification best practices and drive coverage closure.
• Oversee end-to-end DV tasks: design analysis, verification planning, testbench development, simulation, and coverage reporting.
• Drive adoption of formal, emulation, and other advanced DV techniques to improve efficiency and quality.
• Review and optimize test plans, environments, and simulation scripts for scalability and reuse.
• Work with design, architecture, and cross-functional teams to meet milestones; communicate progress, risks, and mitigations.
• Mentor and coach junior engineers to develop technical skills and verification best practices.

Requirements

Must-have technical skills and experience for this role.

• Extensive IP-level design verification experience.
• Strong expertise in SystemVerilog and UVM; experience architecting complex SV/UVM environments.
• Proven experience with coverage-driven verification methodologies and constraint-random testing to achieve coverage closure.
• Strong debugging skills with tools such as Verdi or equivalents.
• Familiarity with formal/static verification techniques.
• Power-aware verification and gate-level simulation (GLS) experience is highly desirable.
• Scripting and automation skills (Python, Perl) for testbench and flow automation.
• Exposure to wireless IPs (Wi‑Fi, modem PHY, DSP blocks) is a plus.
• Excellent communication, collaboration, and technical leadership abilities.

Education Requirements

Required: Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. The posting specifies degree-dependent minimum experience: Bachelor's +8 years, Master's +7 years, PhD +6 years. The role also references an overall experience range of about 12–18 years.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.