Wireless Chip Architect

Job Title

Wireless Chip Architect

Role Summary

Architect connectivity subsystems (Wi‑Fi, Bluetooth, UWB, Cellular IoT) for mixed analog/digital SoCs and lead customer-facing technical engagements from concept through productization. The role partners with product, firmware, design, and validation teams to define architecture, PPA targets, and integration requirements.

Experience Level

Mid-level. The posting expects an experienced engineer with product engineering and tape-out experience; no explicit years-of-experience were stated.

Responsibilities

Own definition and delivery of connectivity subsystem architectures and support their integration into customer SoCs.

• Define connectivity subsystem architecture, feature set, and PPA (power, performance, area) targets.
• Specify system low-power modes and PMU requirements for the subsystem.
• Define HW and SW interfaces, state machines, and operation sequences for connectivity blocks.
• Partition analog and digital domains and coordinate RF/analog integration constraints.
• Lead technical discussions with customers; present architecture options and co-develop joint solutions.
• Support post-tape-out testing, silicon bring-up, production validation, yield analysis, and qualification testing.
• Coordinate cross-functional teams (logic, physical, firmware, validation) to ensure implementation and test coverage.
• Translate customer feedback and market needs into architectural requirements and roadmap inputs.

Requirements

Minimum technical qualifications and skills required for successful performance in the role.

• Deep understanding of full-system SoC architecture, including interactions among connectivity subsystems, processors, memory controllers, power domains, and software stacks.
• Product engineering experience across the full lifecycle, including post tape-out testing, silicon bring-up, productization, and production qualification; proven record of successful tape-outs.
• Experience in system definition for wireless communication systems and familiarity with wireless standards (Wi‑Fi, Bluetooth, Cellular, UWB).
• Experience in ASIC design and architecture and knowledge of VLSI development processes and methods.
• Knowledge of performance and power modeling and analysis techniques.
• Strong technical leadership and communication skills; proven customer-facing experience and ability to influence design decisions.

Nice-to-have:

• RF integration and RF performance optimization experience.
• Experience integrating third-party IP and familiarity with CPU/processor architecture.

Education Requirements

B.Sc. or M.Sc. in Electrical Engineering was specified.

About the Company

Company: Ceva

Headquarters: Herzliya, Israel

Ceva is a semiconductor IP licensor specializing in wireless connectivity and smart sensing technologies. It provides digital signal processors, AI processors, wireless platforms and software for sensor fusion, image enhancement, computer vision, voice input and other AI-enabled functions for connected devices.