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Wafer Architect
Volantis Semiconductor
August 27, 2026
Full-time
Remote friendly (San Francisco, California, United States)
Worldwide
SoC Architecture Jobs, Level - Senior
Job Title
Wafer Architect
Role Summary
Own the logical architecture for the A-0 and A-1 wafer products. Collaborate with XPU/Compute and memory architects to synthesize a coherent wafer-level architecture spanning dies, packages, and system interfaces.
Experience Level
Senior; no specific years of experience listed.
Responsibilities
Primary responsibilities include:
- Define and own the wafer-level logical architecture for A-0 and A-1 products.
- Collaborate with compute (XPU) and memory architects to integrate die- and package-level designs.
- Design architectural partitioning across chiplets, multi-chip modules (MCM), and multi-die systems.
- Analyze and specify memory subsystem interactions for multi-die integration.
- Assess hardware implications of LLM inference workloads at software, system, package, network, and die levels.
- Partition workloads and data movement across chips and packages to meet performance and capacity targets.
- Produce architecture documentation, interface specifications, and handoff artifacts for implementation teams.
Requirements
Must-have technical skills and experience:
- Hands-on experience in the design process of AI chips (GPUs, TPUs, XPUs, or custom ASICs).
- Understanding of memory subsystems and their interactions in multi-die systems.
- Knowledge of LLM inference workloads at the software level and the resulting hardware/system implications.
- Strong collaboration and communication skills for cross-discipline architecture work.
Preferred (nice-to-have):
- Experience with multi-die designs and MCM or chiplet-based architectures.
- Experience partitioning workloads across multiple chips and chip packages.
Education Requirements
Not specified.
About the Company
Company: Volantis Semiconductor
Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.
