VLSI Verification Engineer

Job Title

VLSI Verification Engineer

Role Summary

Join the VLSI team to develop and execute verification for ASIC and FPGA designs used in space computing systems. The role focuses on building UVM-based verification environments, executing verification plans, and collaborating with architecture, design, software and validation teams.

Experience Level

Senior — requires 7+ years of relevant design verification experience.

Responsibilities

Primary responsibilities include:

• Plan and implement UVM verification environments, tests, testbenches, and regressions.
• Generate and execute the Verification Test Plan and Verification Requirement Matrix.
• Develop and maintain verification components and test lists.
• Collaborate with Architecture, Design, Software, and Validation teams to close verification requirements.
• Define and improve design verification methodologies.
• Work on both ASIC and FPGA space-system projects.

Requirements

Must-have:

• 7+ years of design verification experience.
• Proficiency in SystemVerilog and UVM.
• Experience with FPGA/ASIC verification methodologies.
• Experience with FPGA toolchains such as Vivado, Quartus, and VCS.

Nice-to-have:

• Experience validating complex SoC designs.
• Experience with RF communications, DSP algorithms, and high-speed SERDES.
• RTL design experience.
• Experience validating designs for space applications.

Education Requirements

Not specified.

About the Company

Company: Ramon.Space

Ramon.Space develops resilient, software-defined space computing platforms that equip satellites with advanced storage, processing, and connectivity for communications, 5G NTN, earth observation, and space-based data centers, serving commercial and government space missions.