Sr Staff Engineer, STA

Job Title

Sr Staff Engineer, STA

Role Summary

Senior backend design engineer focused on Static Timing Analysis (STA) and logic synthesis. The role owns RTL-to-gate conversion, constraint development, and timing closure to meet performance, power, and area (PPA) targets for complex SoC blocks and full-chip integrations.

Experience Level

Senior — approximately 10–13 years of relevant industry experience.

Responsibilities

Primary responsibilities include synthesis, timing analysis, constraint management, and collaboration with place-and-route to achieve signoff-quality timing closure.

• Execute hierarchical and physical-aware synthesis flows (SystemVerilog RTL → optimized gate-level netlists); perform flat and hierarchical synthesis and floorplan-driven optimizations.
• Perform block-level and full-chip STA across multi-mode multi-corner (MMMC) scenarios and drive timing closure to signoff.
• Collaborate with PNR teams to analyze and optimize clock trees and resolve timing bottlenecks.
• Develop, validate, and maintain comprehensive SDC (constraints) and UPF files for functional and DFT modes.
• Implement and verify UPF-based low-power architectures and multi-voltage domain solutions.
• Use scripting (Tcl, Python, Perl) to automate flows, build utilities, and reduce turnaround time.
• Perform logical equivalence checks (LEC) and manage formal verification between RTL and synthesized netlists.
• Identify design bottlenecks (critical path restructuring, datapath optimizations) and propose PPA-driven solutions.

Requirements

Must-have technical skills, tools experience, and professional capabilities.

• ~10–13 years of hands-on experience in synthesis and STA closure on complex designs.
• Proven experience analyzing clock structures from functional and DFT perspectives and delivering timing closure.
• Experience with high-frequency design synthesis and delivering PPA improvements.
• Familiarity with EDA tools such as Fusion Compiler, Innovus, PrimeTime, Tempus, VCLP, and LEC.
• Strong understanding of static timing analysis, power analysis, and signal integrity concepts.
• Advanced scripting skills in Tcl, Python, or Perl for flow automation.
• Strong problem-solving, attention to detail, and effective cross-functional communication skills.
• Experience mentoring or coaching junior engineers is a plus.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field; or equivalent practical experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.