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Senior Digital Verification Engineer

Renesas
August 25, 2026
Full-time
On-site
Kallithea, Greece
Verification Jobs, Level - Senior

Job Title

Senior Digital Verification Engineer

Role Summary

Lead end-to-end functional verification for complex ASIC/IC blocks and systems. You will own verification strategy, develop UVM-based environments, drive closure of functional and code coverage, and coordinate with architecture, design, and software teams.

This is a technical leadership role that includes mentoring junior engineers and optimizing verification automation and tool selection.

Experience Level

Senior β€” experienced verification engineer with substantial hands-on ASIC/IC verification responsibility.

Responsibilities

Primary responsibilities focus on defining verification strategy, implementing thorough test environments, and achieving verification closure.

  • Architect and execute verification strategies and test plans; implement UVM-based verification environments from scratch.
  • Drive functional and code coverage to closure using constrained-random testing, assertion-based verification (SVA), and formal methods.
  • Review and improve design specifications early to enhance verifiability.
  • Collaborate with global architecture, design, and software teams on hardware/software partitioning and system-level verification.
  • Provide technical leadership and mentorship to junior verification engineers.
  • Evaluate third-party VIP and tools and participate in make/buy decisions to improve engineering efficiency.

Requirements

Must-have technical skills and experience for successful performance in this role.

  • Extensive ASIC/IC digital verification experience with strong mastery of SystemVerilog and UVM.
  • Proven ability to design and set up a UVM testbench from specification to a full verification environment.
  • Proficiency with industry-standard simulators and verification management tools (example: Cadence Xcelium, eManager/vManager).
  • Working knowledge of Verilog and VHDL.
  • Practical experience with functional verification methodologies, assertion-based verification (SVA), formal verification, and regression frameworks.
  • Intermediate to advanced digital design skills to align closely with architecture and design teams.
  • Strong English communication skills (written and verbal) and the ability to influence technical decisions.

Nice-to-have:

  • Experience optimizing automation flows for reusability and performance.
  • Background evaluating VIP and verification tool vendors.
  • Prior mentoring or technical leadership experience.

Education Requirements

Not specified.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-08-20