VLSI Physical Design / APR Engineer

Job Title

VLSI Physical Design / APR Engineer

Role Summary

The VLSI Physical Design / APR Engineer implements and optimizes IC layout from netlist to GDSII, ensuring timing, power, area and manufacturability targets are met for tape-out.

Work with front-end design, DFT, packaging, EDA vendors and foundries on AI vision processor SoCs for edge applications.

Experience Level

Mid-level (approximately 2–7 years of VLSI physical design or related experience)

Responsibilities

Deliver physical implementation and sign-off for SoC blocks and full-chips; collaborate across teams to achieve design closure.

• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verification.
• Drive full flow from netlist to GDSII and support tape-out activities for multi-million-gate SOCs.
• Perform static timing analysis (STA), IR-drop, EM, signal integrity and manufacturability sign-off (DRC/LVS/DFM).
• Analyze and resolve congestion, timing, power integrity and signal integrity issues.
• Create and maintain physical design automation scripts and implementation flows (Tcl scripting for flows).
• Coordinate with front-end design, DFT, package teams, EDA vendors and foundries to ensure design compliance.

Requirements

Key technical skills and practical experience required or strongly preferred.

• 2–7 years of experience in VLSI physical design or related roles (designer to manager range noted).
• Practical tape-out experience on multi-million-gate SoC projects; proven physical closure experience.
• Proficiency with one or more commercial EDA tool suites (Cadence, Synopsys, Mentor/Siemens).
• Experience with STA and sign-off flows, power integrity (IR-drop) and reliability analyses.
• Experience developing and refining design methodology and implementation flows; strong problem-solving skills.
• Good communication and teamwork skills, initiative and fast learning ability.
• Nice-to-have: 10/7/5/3 nm process experience; Perl/Tcl scripting; strong English written/spoken skills.

Education Requirements

Minimum: Masters degree in Electrical Engineering, Computer Engineering, Computer Science or a related technical field (as stated in the posting).

About the Company

Company: Ambarella

Headquarters: Santa Clara, California, USA

Ambarella is a leader in computer vision and video processing technology, providing advanced solutions that enhance the performance of video applications. Focused on quality and innovation, Ambarella develops products for diverse uses, including autonomous vehicles, surveillance systems, and smart cameras, aiming to deliver pristine imagery and efficient compression while minimizing power consumption.