Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

Lead development of RTL-to-GDS physical design (P&R) flows, methodology, and automation for advanced ASIC designs. The role partners with RTL designers, analog/mixed-signal teams, signoff groups, EDA vendors, and PDK/library teams to deliver scalable, high-quality silicon.

This position is expected to work primarily onsite at an HPE office in Sunnyvale, CA.

Experience Level

Senior — typically 7–10+ years of experience in ASIC physical design flows or physical design methodology.

Responsibilities

Principal responsibilities include developing and maintaining P&R flows, providing implementation support, and driving signoff quality.

• Design, maintain, and enhance RTL-to-GDS flows using Cadence Innovus and/or Synopsys Fusion Compiler.
• Define repeatable methodologies for floorplanning, placement, CTS, routing, and ECO flows.
• Automate flow steps and tool runs using Tcl, Python, and Make-based infrastructures.
• Provide hands-on support for floorplan definition, clock topology, power-grid planning, placement optimization, and timing closure.
• Address IR/EM issues, DRC/LVS failures, routing convergence, and signoff discrepancies.
• Improve correlation between implementation tools and signoff tools (PrimeTime, StarRC, Voltus/RedHawk, Calibre).
• Collaborate with EDA vendors, library/PDK teams, and architects to support technology bring-up and design scalability.

Requirements

Must-have technical skills and practical experience.

• 7–10+ years in ASIC physical design flows or physical design methodology.
• Proven expertise with Cadence Innovus and/or Synopsys Fusion Compiler place-and-route flows.
• Solid knowledge of physical design fundamentals: floorplan, placement, CTS, routing, and ECO.
• Strong timing skills (setup/hold closure, OCV/AOCV/POCV, derates) and power/thermal awareness (IR drop, EM).
• Experience with DRC/LVS signoff flows and debugging signoff mismatches.
• Proficient scripting in Tcl and Python and comfortable in Linux shell environments.
• Ability to troubleshoot complex tool, flow, or methodology issues across PD and signoff.

Nice-to-have:

• Experience with advanced process nodes (7 nm, 5 nm, or below).
• Familiarity with UPF/low-power flows, multi-clock-domain and hierarchical P&R.
• Experience with version control (Git/Perforce) and CI automation.
• Experience with extraction and STA signoff tools (StarRC, PrimeTime) and parasitic modeling.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.