VLSI Design Verification Engineer

Job Title

VLSI Design Verification Engineer

Role Summary

Join the VLSI verification team to validate next-generation SoCs and complex IP blocks. The role focuses on applying advanced verification methodologies and working across design, architecture, and post-silicon teams to ensure correctness and reliability.

Experience Level

Mid-level. The posting does not specify required years of experience.

Responsibilities

Responsible for planning, implementing, and executing verification activities for complex SoCs and IPs.

• Develop and execute verification plans and test strategies for SoCs and IP blocks.
• Build and maintain testbenches, assertions, and coverage models.
• Implement coverage-driven and assertion-based verification flows.
• Use AI-assisted tools to accelerate testplan creation, assertion development, and debug.
• Collaborate with architects, RTL designers, and post-silicon validation teams.
• Analyze failures and drive debug to closure to ensure design reliability.

Requirements

Key technical skills and experience expected for successful candidates.

• Must-have: Strong background in digital design and computer architecture.
• Must-have: Hands-on experience with SystemVerilog, UVM, Verilog and coverage methodologies.
• Must-have: Experience programming in C/C++ and strong debugging and analytical skills.
• Nice-to-have: Scripting experience (Perl or Python).
• Nice-to-have: Experience with AI-assisted verification or related automation tools.

Education Requirements

Bachelor's, Master’s, or PhD in Electrical Engineering, Computer Science, or a related technical field.

About the Company

Company: Ambarella

Headquarters: Santa Clara, California, USA

Ambarella is a leader in computer vision and video processing technology, providing advanced solutions that enhance the performance of video applications. Focused on quality and innovation, Ambarella develops products for diverse uses, including autonomous vehicles, surveillance systems, and smart cameras, aiming to deliver pristine imagery and efficient compression while minimizing power consumption.