Senior Verification Engineer – Core Testbench & DV Methodology Lead

Job Title

Senior Verification Engineer – Core Testbench & DV Methodology Lead

Role Summary

Lead ownership of the top-level (core) verification environment, verification methodology, tooling, and CI infrastructure. Evolve the UVM-based core testbench, integrate unit-level VIP, drive functional and code coverage closure, and identify verification gaps between blocks.

Serve as a technical leader and mentor within the verification organization and work with EDA vendors to keep flows and tools current.

Experience Level

Senior — 10+ years of hands-on design verification experience, including significant work on processor cores or complex microarchitectures.

Responsibilities

Primary responsibilities include ownership and continuous improvement of the core testbench and verification flows, coverage closure, cross-unit verification, and technical leadership.

• Own and maintain the top-level UVM core testbench; extend testsuites and integrate unit-level VIP so block-level checkers and coverage are reused.
• Manage functional and code coverage at core level: review nightly results, drive closure, and audit covergroups and tests for intent and quality.
• Identify and close verification gaps at unit boundaries; reconcile assume/guarantee relationships across testbenches.
• Maintain and improve verification flows (compile, coverage collection, regressions) and CI; update compile configs and keep regressions efficient and reliable.
• Drive upgrades to flows and scripts, liaise with EDA vendors, and adopt next-generation coverage/simulator capabilities.
• Provide technical leadership: review testbench architectures, set verification standards, and mentor engineers on coverage-driven and assertion-based verification.

Requirements

Must-have technical skills and experience to perform the role.

• Significant experience verifying processor cores or complex microarchitecture; RISC-V experience preferred.
• Expert SystemVerilog and UVM; experience building reusable, configurable, multi-agent environments and integration testbenches.
• Strong functional-coverage and verification-planning skills; experienced in coverage-driven verification.
• Deep hands-on with Questa (primary simulator) and a waveform/debug tool (Visualizer / Verdi); familiarity with VCS/Xcelium is a plus.
• Strong scripting skills (Python) and practical experience with Bash/Tcl; ownership of CI/CD and regression infrastructure.
• Proficient with assertion-based verification (SVA) and reasoning about cross-block assume/guarantee contracts.

Nice-to-have:

• Formal verification experience.
• Experience with emulation platforms (Veloce, ZeBu).
• Knowledge of core/bus interface protocols (e.g., AXI, CHI).

Education Requirements

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field (specified in the posting).

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.