Senior Formal Verification Engineer – Vector Unit (VU)

Job Title

Senior Formal Verification Engineer – Vector Unit (VU)

Role Summary

Senior individual contributor responsible for owning the formal verification environment for a next-generation Out-of-Order RISC-V Vector Unit. You will design scalable formal testbenches, write mathematical properties, and ensure algorithmic and architectural correctness of vector execution and arithmetic blocks.

Work closely with VU microarchitects and simulation engineers to find corner-case bugs and achieve formal sign-off. Role is based in Barcelona with a hybrid cadence (4 days in office, 1 WFH).

Experience Level

Senior. Typical guidance: 5+ years of production-grade hardware verification applying formal methods, or Ph.D. plus 1–3 years industry experience.

Responsibilities

Primary responsibilities cover block-level formal verification, proof convergence, and mentoring on formal-friendly design.

• Design, deploy, and maintain formal verification environments for Vector Unit sub-blocks (e.g., execution pipelines, register file/rename interfaces, floating-point units).
• Implement word-level modeling, bit-blasting, and algebraic-rewriting strategies to verify IEEE-754 floating-point and integer vector arithmetic.
• Diagnose and resolve proof-convergence failures, over-constraints, and state-space explosion using reduction techniques (case-splitting, black-boxing, abstraction).
• Develop formal proofs that the VU pipeline complies with the RISC-V Vector extension specification.
• Define clear simulation/formal boundaries in collaboration with simulation engineers to maximize bug discovery and eliminate coverage gaps.
• Partner with microarchitects during RTL development to encourage formal-friendly coding and structural patterns.
• Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers; establish block-level assertion best practices.
• Translate formal counter-examples into actionable bug reports and verification tasks for designers.

Requirements

Must-have technical skills, tools, and collaboration style. Education requirements are summarized in the Education Requirements section below.

• 5+ years production hardware verification applying formal to CPU/GPU/DSP pipelines (or Ph.D. + 1–3 years).
• Proven specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling; familiarity with control-path formal techniques (liveness, safety).
• Experience with high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware; Out-of-Order execution experience is a plus.
• Proficient with commercial formal tools and datapath/mathematical apps (examples: JasperGold, VC Formal, OneSpin).
• Native fluency in SystemVerilog and SystemVerilog Assertions (SVA); scripting skills in Python, Tcl, or Bash for testbench automation.
• Strong collaboration and communication skills; ability to work within a localized block-level team and translate proofs into design fixes.

Nice-to-have:

• RISC-V core verification experience and familiarity with RISC-V Vector (V) and Floating-Point extension ecosystems.
• Experience with emulation platforms (Veloce, ZeBu) and common interconnects (AXI, CHI).

Education Requirements

B.S. or M.S. in Computer Engineering, Electrical Engineering, or Computer Science; or a Ph.D. with a research focus on formal methods or computer arithmetic. Equivalent practical industry experience is acceptable.

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.