VLSI CAD Engineer

Job Title

VLSI CAD Engineer

Role Summary

Work on synthesis flow and CAD tool infrastructure for Apple silicon SoC partitions. The role focuses on optimizing synthesis processes, debugging EDA tool issues, validating Power/Performance/Area (PPA) impacts, and integrating improvements into production flows.

Full-time, 40 hours/week, based in Cupertino, CA; collaboration with vendors and cross-functional teams (including Logic Equivalence and PnR teams) is required.

Experience Level

Mid-level. The posting does not list explicit years of experience; responsibilities assume demonstrated hands-on experience with synthesis and EDA tool automation.

Responsibilities

Primary responsibilities include maintaining and improving synthesis flows, performing experiments, and automating workflows to improve design convergence and PPA.

• Maintain and optimize the synthesis flow for SoC partitions using industry EDA tools (example: Cadence Genus).
• Troubleshoot and resolve CAD/EDA tool issues to achieve timing closure and improve quality-of-results.
• Tune synthesis attributes and plugins; analyze their impact on Power, Performance, and Area (PPA).
• Run synthesis and place-and-route (PnR) experiments to validate features before production rollout and ensure post-synthesis to post-PnR correlation.
• Develop and maintain automation scripts to streamline synthesis workflows (Python, Tel scripting).
• Collaborate with vendor teams and cross-functional groups (e.g., Logic Equivalence) to validate features and ensure logical equivalence to RTL.
• Perform RTL analysis and correlation studies to assess implementation effects and identify optimization opportunities.
• Monitor and iterate on synthesis methodology to keep flows efficient across process nodes.

Requirements

Must-have technical skills and experience; preferred qualifications are not specified.

• Hands-on experience optimizing synthesis EDA tools and CAD flows to reach timing closure and improve QoR.
• Practical experience with synthesis tools (for example Cadence Genus) or equivalent commercial synthesis tools.
• Proficiency in scripting for flow automation and utilities (Tel scripting and Python).
• Experience with SoC methodology, Place-and-Route experimentation, and validating physical implementation feasibility.
• Experience analyzing RTL and correlating RTL-to-post-synthesis and post-PnR results.
• Experience applying PPA optimization techniques and evaluating feature impacts on PPA metrics.
• Familiarity with Logic Equivalence Checking (LEC) or cross-functional verification practices.
• Background in developing and refining synthesis methodology, proactive debugging, and tool-chain troubleshooting.

Education Requirements

Master's degree or foreign equivalent in Electrical Engineering or a related field. The posting states "Education and/or experience must include" the listed technical skills (i.e., a combination of degree and relevant practical experience is acceptable).

About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.