Video Codec Design Engineer (up to Staff)

Job Title

Video Codec Design Engineer (up to Staff)

Role Summary

Join the SoC design team to architect and implement hardware video encoder and decoder IP for high-performance, low-power semiconductor products across IoT, mobile, automotive, and embedded markets.

Responsible for microarchitecture, modeling, RTL implementation, optimization, and cross-functional integration to meet performance, area, and power targets.

Experience Level

Senior level. Typical experience guidance per internal minimums: Bachelor's +4 years, Master's +3 years, PhD +2 years. Role may be filled at Staff level depending on experience.

Responsibilities

Primary responsibilities include designing, modeling, integrating, and validating video codec hardware and ensuring its delivery within SoC constraints.

• Architect, design, and optimize hardware blocks for video encode/decode (motion estimation/compensation, transform/quantization, entropy coding, in-loop filters, rate control).
• Translate video standards (H.264/AVC, H.265/HEVC, AV1, VVC, etc.) into scalable, configurable microarchitectures and hardware algorithms.
• Build C/C++/SystemC models for performance, accuracy, and power estimation and perform algorithm-to-hardware decomposition.
• Evaluate codec KPIs (throughput, latency, memory bandwidth, quality) with systems and architecture teams.
• Define test plans, functional coverage, and debug infrastructure with verification teams for pre-silicon validation.
• Integrate codec IP into SoC subsystems, coordinating memory subsystems, firmware interfaces, and interconnects.
• Work with physical design to meet PPA targets through timing-aware microarchitecture and pipeline/power planning.
• Support post-silicon bring-up, analyze chip performance, and recommend architectural or firmware fixes.

Requirements

Must-have technical skills and experience; degrees and formal education requirements are summarized separately under Education Requirements.

• Strong understanding of video compression algorithms and components (transform coding, motion estimation/compensation, loop filters, entropy coding).
• Experience in RTL design (Verilog/SystemVerilog), microarchitecture and pipeline design, and hardware performance optimization.
• Proficiency in C/C++/Python/SystemC for modeling and architectural exploration.
• Solid grasp of SoC design: memory hierarchy, interconnect, bandwidth constraints, and power/performance trade-offs.
• Experience collaborating with verification, physical design, and firmware/software teams.
• Preferred (nice-to-have): contributions to or experience with modern video coding standards (HEVC, VVC, AV1, VP9), scripting experience, and FPGA flow exposure.

Education Requirements

Minimum qualifications list a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related science/engineering field. The posting specifies experience thresholds tied to degree: Bachelor's +4 years, Master's +3 years, PhD +2 years. Equivalent practical experience is accepted where indicated.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.