Verification Staff Engineer - Analog Mixed-Signal

Job Title

Verification Staff Engineer - Analog Mixed-Signal

Role Summary

Join the analog/mixed-signal (AMS) verification team to plan and execute verification activities that support first-pass silicon success for AMS integrated circuits and subsystems. The role focuses on mixed-signal verification strategy, environment and testbench development, and cross-functional technical collaboration.

Experience Level

Senior - typically aligned with candidates having 5+ years of verification experience in advanced methodologies and mixed-signal designs.

Responsibilities

Primary responsibilities include ownership of verification tasks, creating reusable verification components, and collaborating across design and validation teams.

• Develop and execute verification plans to meet performance, power, and schedule targets.
• Design and maintain mixed-signal verification environments, testbenches, regressions, checkers, and coverage metrics.
• Implement verification IP using object-oriented principles and UVM methodologies.
• Debug RTL for design intent and verify AMS interactions between analog and digital blocks.
• Extract features from analog schematics to derive verification tests and metrics.
• Participate in technical reviews with design, systems, test, and validation teams.
• Identify verification risks and contribute to mitigation plans to ensure verification completeness.
• Provide technical guidance and documentation for the verification team; promote reuse and efficiency improvements.

Requirements

Must-have technical skills and competencies; items listed as "nice-to-have" are desirable but not mandatory.

• Must-have: 5+ years experience owning verification of complex digital and mixed-signal designs (experience expectation noted in Experience Level).
• Must-have: Strong fundamentals in analog and mixed-signal circuit concepts and topologies.
• Must-have: Strong proficiency in SystemVerilog and advanced verification methodologies including assertions, constrained randomization, metric-driven verification, and UVM.
• Must-have: Familiarity with Verilog RTL and ASIC design methodology; ability to write and debug testbenches and simulations.
• Must-have: Experience with mixed-signal verification and simulation tools such as Cadence Virtuoso, xCelium, Incisive, vManager, IMC (or similar flows).
• Must-have: Ability to read analog schematics and extract main functionality for verification purposes.
• Must-have: Scripting skills for UNIX shell, Perl, and TCL to automate regressions and tool flows.
• Must-have: Experience in verification planning, feature extraction, coverage and checker development, simulation and debugging.
• Nice-to-have: Behavioral modelling of analog blocks using SystemVerilog RNM and Verilog-AMS; experience modelling mixed-signal blocks (bias networks, regulators, bandgaps, amplifiers, converters, etc.).
• Nice-to-have: Specific experience modelling power converters.

Education Requirements

Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or equivalent; or equivalent practical experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.