Silicon Packaging Engineer (SIPI)

Job Title

Silicon Packaging Engineer (SIPI)

Role Summary

Lead signal integrity and power integrity (SI/PI) chip-package-system co-design for next-generation AI accelerator and high-performance computing silicon using 2.5D/3D heterogeneous packaging. Collaborate with ASIC architecture, physical design, package layout, PCB, and foundry/OSAT partners to ensure high-speed interfaces and power delivery meet performance, margin, and reliability targets before tape-out.

Experience Level

Senior - typically requires 8+ years of relevant SI/PI simulation, analysis, and validation experience.

Responsibilities

Primary responsibilities include:

• Drive SI/PI requirements into chip floorplan, bump map, power tree, and net topology for 2.5D/3D package technology.
• Partner on die-package-board co-optimization: bump assignment, escape routing, and stack-up decisions across multiple chiplets.
• Lead package SI/PI design activities: substrate/interposer stack-up, material selection, design guides, layout review, and post-layout sign-off.
• Design and margin high-speed channels (HBM/HBM4/UHBM, UCIe, PCIe Gen5/Gen6, Ethernet SerDes, next‑generation memory interfaces).
• Perform PDN AC+DC analysis: impedance targeting, decoupling optimization, IR drop, and di/dt noise.
• Develop and run pre-layout and post-layout SI/PI simulation flows; build models and improve flows through automation and correlation.
• Maintain interface timing, voltage, and noise budgets across silicon IO PHY, package, and board.
• Define SI/PI validation methodology and engineering test plans; execute post-silicon validation and correlate lab measurements with simulation.
• Support SI/PI failure analysis and drive corrective design guidance into the flow.
• Engage foundries, OSATs, and memory suppliers on interconnect and die-stacking standards.

Requirements

Must-have:

• 8+ years of experience in signal integrity analysis, simulation, and measurement.
• Proficiency with HFSS, Cadence Sigrity, Hspice, or comparable SI/PI simulation tools.
• Strong understanding of impedance control, transmission line theory, and PDN characterization.
• Experience with 2.5D/3D package design (silicon interposer, silicon bridge, die stacking) and SIPI modeling in frequency and time domains.
• Expertise in SI/PI for high-speed interconnects (HBMx, die-to-die links, Ethernet, PCIe, SerDes).
• Familiarity with post-silicon test environments for memory and high-speed SerDes.
• Experience collaborating with cross-functional teams across architecture, physical design, package, PCB, and system integration.
• Ability to develop automated simulation flows and perform model correlation to improve accuracy and turnaround.

Nice-to-have:

• Experience with Ansys SIwave, PowerSI, Keysight ADS, 3D layout tools, or similar toolchains.
• Background in computational electromagnetics, transmission line theory, or advanced PDN modeling.
• Experience with consumer hardware bring-up, CAD tools, and constraint management.
• Familiarity with high-speed protocol implementations (MIPI, USB) and advanced memory interfaces.

Education Requirements

Required: Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Preferred: Master's degree or PhD in Electrical Engineering, Physics, Mathematics, or a related field.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.