Verification Lead (Lead DV)

Job Title

Verification Lead (Lead DV)

Role Summary

Lead end-to-end design verification for a first-of-its-kind chiplet, defining strategy, methodology, and signoff criteria from block level to full-chip. You will build the verification infrastructure, own hardware-assisted verification, and verify performance, mixed-signal interactions, and low-power signoff.

This is a founding verification hire responsible for establishing coverage-driven methodology and a scalable regression/CI practice while growing a DV team across multiple subsystems.

Experience Level

Senior — 10+ years of ASIC/SoC verification experience with demonstrated team leadership and delivery from plan to tapeout.

Responsibilities

Primary ownership of verification strategy, infrastructure, and delivery for a complex chiplet and its subsystems.

• Define verification plan, functional and code coverage model, UVM architecture, and signoff criteria from block to full-chip.
• Design and deploy regression/CI infrastructure and nightly runs prior to RTL availability; ensure triage automation and scalable grid execution.
• Verify in-house engines against algorithmic golden models, including programmable error injection and error-pattern coverage.
• Define and own hardware-assisted verification methodology (emulation and FPGA prototyping) and manage bring-up.
• Implement VIP and compliance testing for link protocols (UCIe and similar): link training, loopback, lane-repair, and bit-exact transparency tests.
• Perform performance and throughput verification, including system-level scenarios and corner cases.
• Lead UVM register verification, firmware co-simulation, and MCU boot-flow validation.
• Coordinate mixed-signal co-simulation and gate-level / low-power (UPF) verification as part of signoff.
• Recruit, mentor, and grow the DV team across FEC, UCIe, MCU, datapath, and full-chip domains.

Requirements

Concise list of required skills and experience, plus preferred capabilities.

Must-have:

• 10+ years ASIC/SoC verification experience with team leadership on at least one complex SoC from plan to tapeout.
• Deep expertise in UVM/SystemVerilog, coverage-driven and constrained-random verification methodologies.
• Hands-on hardware-assisted verification experience with emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).
• Experience with mixed-signal verification (Verilog-AMS or SystemVerilog behavioral models) and gate-level / UPF signoff flows.
• Proven delivery of verification for large digital SoCs/subsystems, including interconnect fabrics and full-chip closure.
• Experience building regression/CI at scale, coverage closure processes, and triage automation.

Nice-to-have:

• Experience with high-speed SerDes, PAM4, FEC/coding (Reed-Solomon) verification.
• UCIe, PCIe/CXL, Ethernet, UALink, or comparable die-to-die/link-layer VIP and compliance experience.
• Past work on NICs, Ethernet/IB switches, cache-coherency (multi-core/coherent fabric) verification.
• Low-power methodology, performance-verification experience, formal verification for control logic, or portable stimulus experience.

Education Requirements

Not specified.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.