Verification Lead - IP UVM System Verilog

Job Title

Verification Lead - IP UVM System Verilog

Role Summary

Lead a team of verification engineers to plan, develop, and execute IP-level verification for complex digital semiconductor IPs using UVM and SystemVerilog. Deliver verification closure, ensure functional coverage, and sign off on verification deliverables to meet project timelines and quality targets.

Experience Level

Senior-level. Years of experience not specified; role requires prior experience leading verification teams and driving verification closure on ASIC/SoC or IP projects.

Responsibilities

Accountabilities for the verification lead:

• Lead end-to-end IP verification: planning, environment development, execution, and closure.
• Design and implement advanced UVM-based testbenches and verification environments.
• Define, review, and maintain verification plans, test plans, and coverage models.
• Develop reusable verification components, sequences, scoreboards, and utilities in SystemVerilog/UVM.
• Drive functional coverage closure; analyze coverage holes and improve tests.
• Debug complex simulation failures and coordinate root-cause analysis with design teams.
• Collaborate with design, architecture, and physical design teams to align on specifications and schedules.
• Mentor and guide junior and mid-level verification engineers; review verification deliverables and sign off.
• Contribute to process and methodology improvements for verification efficiency.

Requirements

Core technical requirements and preferred skills.

• Strong hands-on experience in digital IP/SoC functional verification.
• Proficiency in SystemVerilog and UVM-based verification methodology.
• Solid understanding of constrained-random verification and functional coverage.
• Experience with assertion-based verification (SVA).
• Familiarity with industry-standard simulators (e.g., VCS, Xcelium, Questasim) and waveform/debug tools.
• Experience leading or mentoring a verification team and driving verification closure.
• Knowledge of standard bus protocols (AXI, AHB, APB, PCIe, USB, or similar).

Nice-to-have:

• Exposure to formal verification techniques.
• Experience with scripting for automation (Python, Perl, or similar).

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, VLSI, Computer Engineering, or a related discipline.

About the Company

Company: Vitestork Consulting

Headquarters: Hyderabad, Telangana, India

Technology consulting firm specializing in VLSI and semiconductor engineering services, offering expert staffing and project-based solutions for electronics and chip design clients.