Senior Staff Physical Design Engineer
SynopsysJob Title
Senior Staff Physical Design Engineer
Role Summary
Senior physical design engineer responsible for timing closure, signoff readiness, and physical implementation methodologies for advanced-node ASICs (5nm, 3nm and below). Works across block, subsystem, and full-chip scopes, develops automation and flows, and collaborates with front-end, verification, and CAD teams to deliver silicon on schedule.
Experience Level
Senior-level; typically requires 8+ years of hands-on ASIC physical design and timing closure experience.
Responsibilities
Primary responsibilities include implementation, flow development, automation, signoff, and cross-team collaboration.
- Drive timing closure and signoff readiness for advanced-node designs (5nm, 3nm, and below) at block, subsystem, and full-chip levels.
- Develop and refine physical design methodologies and automation using TCL, Python, and Perl.
- Perform static timing analysis, clock-tree synthesis, and ECO implementation using PrimeTime, ICC2, Fusion Compiler, and other signoff tools.
- Analyze design data and PPA trends to identify bottlenecks and optimize workflows.
- Collaborate with front-end design, verification, and CAD teams to ensure successful silicon delivery on schedule.
- Contribute to AI/ML-driven design optimization and data-driven engineering initiatives.
- Troubleshoot congestion, power integrity, and multi-corner timing convergence; create reusable technical solutions.
Requirements
Must-have technical skills and experience; nice-to-have items listed separately.
- Must-have: 8+ years of ASIC physical design, implementation, and timing closure experience.
- Must-have: Deep experience with Synopsys ICC2, Fusion Compiler, or Cadence Innovus.
- Must-have: Strong working knowledge of timing, power, and signoff tools such as PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, or Conformal.
- Must-have: Proven ability to develop flows and automation using TCL, Python, Perl, or similar scripting languages.
- Must-have: Experience with advanced-node semiconductor design at 7nm or below.
- Nice-to-have: Exposure to machine learning or AI-assisted design optimization.
- Nice-to-have: Experience scaling methodologies across teams and mentoring peers.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
