R&D Engineering, Director

Job Title

R&D Engineering, Director

Role Summary

Lead the Digital Methodology Center of Excellence efforts for Design-for-Test (DFT) methodology, deployment, and customer engagements at Synopsys. Serve as the technical lead for TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions, driving methodology adoption across products and strategic accounts.

Experience Level

Senior - 15+ years of experience in the Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.

Responsibilities

Provide technical leadership for DFT methodology, architecture, and customer deployments; mentor engineers and coordinate cross-functional initiatives.

• Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
• Act as subject matter expert for TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
• Lead deployment of advanced DFT architectures: scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrappers, IJTAG infrastructures, and embedded test.
• Architect scalable test access and instrumentation networks using JTAG, AC JTAG, IJTAG, and IEEE 1500 standards.
• Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
• Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across programs and business units.
• Collaborate with R&D to influence product capabilities and roadmap priorities; provide technical leadership in strategic customer engagements.
• Mentor and develop engineering teams to build DFT expertise across the organization.

Requirements

Must-have technical qualifications are listed first; preferred skills follow.

• Must-have: 15+ years in the Semiconductor or EDA industry focused on DFT, ATPG, and manufacturing test methodologies.
• Must-have: Demonstrated expertise architecting and implementing DFT solutions for large-scale ASICs and SoCs.
• Must-have: Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
• Must-have: Deep knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, and fault models (stuck-at, transition, path-delay, bridge, cell-aware).
• Must-have: Experience with coverage analysis, pattern-count reduction, and test-cost optimization.
• Must-have: Experience developing JTAG/TAP architectures, boundary-scan networks, IJTAG instrumentation, and embedded instrument access solutions.
• Must-have: Experience deploying and integrating DFT IP such as embedded compression, OCC, LBIST, TAP controllers, TDR networks, and IEEE 1500 wrappers.
• Must-have: Strong understanding of RTL-to-GDSII flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
• Must-have: Proficiency with scripting for methodology development and automation (Tcl, Python, Perl, Shell, or similar).

Nice-to-have:

• Recognized expert in DFT architecture and enterprise-wide standards/signoff methodologies.
• Experience with advanced-node ASICs, multi-billion-gate SoCs, silicon bring-up, diagnosis, and production ramp.
• Knowledge of functional safety standards and automotive test requirements.
• Experience in customer-facing methodology leadership, consulting, publications, patents, or conference presentations.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.