Verification Engineering Lead/Manager

Job Title

Verification Engineering Lead/Manager

Role Summary

Lead verification efforts for mixed-signal SoCs, focusing on UVM-based chip‑level testbenches for multi-core, multi-threaded processor subsystems. Responsible for verification sign-off of functionality, performance and power, and for driving silicon-to-production readiness.

Experience Level

Senior. See Education Requirements for degree-and-experience guidance.

Responsibilities

Lead and manage verification activities and personnel to achieve tape-out and production goals; define and execute verification plans and metrics.

• Lead SOC and mixed-signal verification team; mentor engineers and manage tasks to deliver on schedule.
• Develop and sign off test plans, directed and constrained-random test cases, and coverage goals.
• Architect chip-level UVM testbenches for ARM/RISC‑V based SoCs and high-speed interfaces.
• Run and maintain daily/weekly regressions; publish results and debug failures with design teams.
• Integrate and run BIST and DFT gate-level simulations; perform RTL and gate-level functional/code/line/toggle coverage analysis.
• Work with systems and test engineering to validate parts and support production release.

Requirements

Core technical and leadership requirements. Education requirements are listed separately below.

• Proven experience managing or leading a verification team for ASIC/SoC projects.
• Strong proficiency in Verilog/SystemVerilog and UVM (OVM knowledge acceptable).
• Experience with assertions, constrained-random verification and functional/code coverage methodologies.
• Familiarity with AMBA protocols (AHB/AXI/APB) and processor-based SoC architecture (ARM or RISC‑V).
• Experience verifying high-speed interfaces such as PCIe, MIPI, USB, Ethernet, DDR and peripheral interfaces (SDIO, UART, I2C, SPI, etc.).
• Strong scripting and automation skills: Python, Perl, TCL, Linux shell scripting.
• Experience with sign-off simulators and debug tools (e.g., Verdi/Siloti) and mixed-signal/AMS simulation flows.
• Analytical debugging, technical documentation, and strong communication skills.
• Ability to drive coverage targets (95%+ goals) and work under schedule pressure.

Nice-to-have: UPF awareness, AMS/analog testbench development, experience with UCIe or other advanced interconnects.

Education Requirements

BS in Electrical Engineering with 3+ years of experience, or MS in Electrical Engineering with 1+ years of experience. No other degrees or equivalents specified in the source.

About the Company

Company: Omni Design Technologies

Headquarters: Hyderabad, India

Omni Design Technologies specializes in the development of advanced solutions for electronic design automation, focusing on ASIC and FPGA verification processes. The company provides high-quality verification tools and resources for engineers in the semiconductor industry, ensuring efficient design and reliable performance.