Verification Engineer (UVM/SystemVerilog)

Job Title

Verification Engineer (UVM/SystemVerilog)

Role Summary

Indotronix Avani Group is seeking an onsite Verification Engineer to develop and execute functional verification for digital ASIC/FPGA designs using SystemVerilog and UVM. The engineer will work on verification planning, constrained-random/self-checking testbench development, debug, and coverage closure.

Experience Level

Senior-level. The role expects experienced verification engineers, typically 7+ years of verification experience; 5+ years may be acceptable with strong UVM background.

Responsibilities

Deliver verification solutions for digital designs and take ownership of verification activities from planning through closure.

• Design and implement SystemVerilog/UVM testbenches and verification IP.
• Develop constrained-random and self-checking tests; implement assertions and checkers.
• Create and execute verification plans; drive coverage closure (functional and code coverage).
• Debug failures in simulation and contribute to root-cause analysis with design teams.
• Produce clear technical documentation and verification reports.
• Work independently with minimal oversight and coordinate with cross-functional teams.

Requirements

Key skills and qualifications required for successful performance in the role.

• Must-have: Active U.S. Secret security clearance at start.
• Must-have: Strong SystemVerilog and UVM experience.
• Must-have: 7+ years of verification experience (5+ acceptable with solid UVM depth).
• Must-have: Experience with constrained-random, self-checking testbenches, assertions, and coverage methodologies.
• Must-have: Proven debugging skills and experience driving coverage closure.
• Strong written and verbal communication; ability to produce high-quality technical documentation.
• Onsite presence in El Segundo, CA; ability to work the listed shift hours (first shift).

Education Requirements

Education/experience typically from an accredited program in engineering, computer science, mathematics, physics or chemistry (e.g., Bachelor's). The posting also documents advanced-degree equivalencies (Master's, PhD) with corresponding reduced years-of-experience examples and notes ABET accreditation is preferred but not required. Equivalent practical experience may be considered.

About the Company

Company: Indotronix Avani Group

Engineering services firm providing FPGA/ASIC design and verification support for high‑reliability and military systems (e.g., GPS). Offers contract engineering across requirements capture, digital architecture, RTL design (VHDL/Verilog), verification (SystemVerilog/UVM), timing closure, and lab integration in secure environments.