Senior ASIC Design Verification Engineer

Job Title

Senior ASIC Design Verification Engineer

Role Summary

Join the ASIC design verification team to define and execute verification strategies that ensure next-generation firewall ASICs meet product requirements for functionality, performance, and reliability. The role focuses on pre-silicon verification (simulation, emulation, formal) and silicon validation, working closely with architects, designers, and software engineers.

This is an office-based role (expectation: four days per week in Santa Clara) with hands-on ownership of verification plans, test infrastructure, and automation.

Experience Level

Senior-level. Minimum 5 years of ASIC design verification experience (per job posting).

Responsibilities

Primary responsibilities include planning, implementing, and executing verification activities across multiple platforms and collaborating with cross-functional teams.

• Define verification methodologies and architect SystemVerilog/UVM testbenches.
• Develop and execute simulation, emulation, and formal verification test plans; specify and close functional coverage.
• Create constrained-random tests, self-checking infrastructure, reference models, and scoreboards.
• Develop emulation flows, run and debug emulation tests, and support silicon validation and bring-up.
• Implement automation for regression, triage, metrics collection, and coverage closure using Python and scripting tools.
• Debug complex failures, drive issue resolution across design, software, and system teams, and report verification status.
• Drive continuous improvement of tools, methodologies, and verification velocity.

Requirements

Must-have technical skills and demonstrated experience are listed below; preferred qualifications follow.

• Must-have: Minimum 5 years in ASIC design verification with track record of taking ASICs from concept to production.
• Must-have: Expertise in SystemVerilog and UVM.
• Must-have: Experience defining test plans, adversarial testing, and developing functional coverage models.
• Must-have: Ability to build scalable, self-checking testbenches and reusable constrained-random tests; strong debug and coverage-closure skills.
• Must-have: Proficiency in scripting and automation (Python, Perl, UNIX shell) to support regression and verification workflows.
• Preferred: Experience with networking/cybersecurity domains, formal property verification, silicon bring-up and validation, emulation flows.
• Preferred: Experience writing models or driver code in C/C++ and producing modular verification tools.
• Preferred: Demonstrated ownership, leadership, collaboration, and clear communication skills.

Education Requirements

BS in Electrical Engineering, Computer Engineering, or Computer Science required, or equivalent military experience. MS in Electrical Engineering (MSEE) preferred.

About the Company

Company: Palo Alto Networks

Headquarters: Santa Clara, California, United States

Global cybersecurity company that develops network and cloud security products, including next-generation firewalls, endpoint protection, threat intelligence, and AI-driven security platforms for enterprises and service providers.