Verification Engineer

Job Title

Verification Engineer

Role Summary

Join an ASIC design verification team focused on pre-silicon verification for complex SoCs and subsystems. The role owns verification strategy, develops SystemVerilog/UVM testbenches, runs simulations and analyses, and drives verification closure across design and architecture teams.

The team uses coverage-driven verification, formal methods, and industry-standard EDA tools to validate functionality, performance, and power for next-generation semiconductor products.

Experience Level

Mid-level role. Minimum 6+ years of experience in ASIC/FPGA design verification; candidates with roughly 3–7 years typically fit this level.

Responsibilities

Key responsibilities include defining and executing verification efforts across blocks, subsystems, and SoCs.

• Define and implement scalable, reusable verification plans, testbenches, and environments to meet coverage goals and microarchitecture specs.
• Lead verification execution: create detailed test plans, run technical reviews with design and architecture teams, and drive proof-of-coverage activities.
• Implement and run simulation models to verify design functionality, analyze power and performance, and identify bugs.
• Replicate, root-cause, and debug pre-silicon failures; propose and implement fixes.
• Collaborate with SoC architects, micro-architects, RTL developers, post-silicon and physical design teams to verify complex features.
• Improve verification infrastructure and methodologies; adopt lessons from post-silicon validation to update test plans.
• Mentor and guide junior engineers; provide technical leadership within the verification team.

Requirements

Must-have technical skills and experience for initial consideration; preferred items listed separately.

• 6+ years of ASIC/FPGA design verification experience.
• Proven expertise in SystemVerilog and UVM; strong understanding of OOP principles applied to verification.
• Experience developing UVM- and/or formal-based verification architectures and methodologies.
• Familiarity with industry-standard protocols such as AMBA (AXI/AXI‑S/CHI) and low-speed interfaces (UART, SPI, I2C/I3C).
• Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
• Coverage-driven verification, constrained-random testing, and strong debug skills.
• Proficiency with scripting languages for automation and debug.

Nice-to-have / preferred:

• Overall 8+ years of relevant experience preferred.
• Experience with processor-based verification using C/C++ within UVM environments.
• Experience validating IPs and SoCs end-to-end: test plan, testbench, tests, debugging, coverage and analysis.
• Low-power verification experience (e.g., UPF) and familiarity with protocols such as DDR, PCIe, Ethernet, UCIe.
• Experience integrating 3rd-party VIPs, building reusable testbenches for subsystems and SoCs.
• Experience with formal verification techniques and tools is an asset.

Education Requirements

Bachelor's degree in electrical engineering, computer engineering, computer science, or another STEM field is required. A graduate or post-graduate degree in a relevant STEM field is preferred where noted.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.