Verification Design Engineer
SynopsysJob Title
Verification Design Engineer
Role Summary
Lead verification efforts for PHY and high-speed interface IP. Work on verification strategy, SystemVerilog/UVM testbenches, coverage, and debug while collaborating with architecture, RTL design, firmware, and implementation teams.
Experience Level
Senior-level. Expect 10–12+ years of relevant ASIC/IP verification experience.
Responsibilities
Primary responsibilities include:
- Develop verification strategies for PHY, DDRIO, UCIe, SERDES and other high-speed interface IP.
- Architect and implement SystemVerilog/UVM testbenches and reusable verification components.
- Create directed and constrained-random tests, assertions, and functional coverage models.
- Drive functional and code coverage closure, regression analysis, and verification signoff.
- Debug RTL, protocol, testbench, and system-level issues in partnership with design engineers.
- Verify block- and subsystem-level functionality including resets, clocking, low-power behavior, and error scenarios.
- Collaborate closely with RTL design, architecture, firmware, modeling, and implementation teams.
- Mentor engineers and help advance verification methodology and best practices.
Requirements
Must-have technical skills and experience:
- Extensive ASIC/IP design verification experience.
- Advanced proficiency with SystemVerilog and UVM.
- Experience developing verification environments, test plans, assertions, functional coverage, and constrained-random tests.
- Strong RTL and waveform debugging skills.
- Experience with high-speed interface technologies such as PHY, DDR/DDRIO, UCIe, and SERDES; familiarity with PCIe and CXL is beneficial.
- Understanding of the complete ASIC/IP development and verification lifecycle.
- Strong analytical, problem-solving, and communication skills.
Nice-to-have:
- Experience verifying complex IP at block and subsystem level.
- Coverage-driven verification and verification closure experience.
- Familiarity with low-power verification, clock/reset verification, and protocol checking.
- Experience with industry-standard simulation, debug, coverage, and verification tools.
- Experience mentoring engineers or providing technical verification leadership.
Education Requirements
BS in Electrical Engineering, Computer Engineering, or a related field with 12+ years of relevant experience, or MS with 10+ years of relevant experience.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
