UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

Join Draper’s Digital Design Team to develop verification strategies and environments for FPGA and ASIC digital designs targeting embedded security, cryptography, signal/image processing, navigation, and communications. Work across multi-disciplinary teams to author and execute verification plans, close functional coverage, and support RTL and system-level integration.

This role supports remote work from anywhere and requires collaboration with designers, architects, and verification engineers to deliver production-ready hardware and verification infrastructure.

Experience Level

Mid-level. Typical experience: 3–5 years with a bachelor’s degree, or 0–2 years with a master’s degree in integrated circuits/ASIC hardware engineering or a related field (see Education Requirements for degree details).

Responsibilities

Primary verification and hardware design responsibilities include:

• Develop verification strategies and detailed verification/test plans for block- and chip-level designs.
• Author and maintain UVM/UVMF testbenches, including UVM agents for proprietary buses and instantiation of VIPs for industry-standard buses.
• Implement constrained-random tests, covergroups, and work to achieve functional- and code-coverage closure.
• Use simulators and formal analysis tools to find and debug issues; work with RTL designers to resolve simulation failures.
• Perform code reviews and mentor junior engineers on verification best practices.
• Design and simulate transistor- and RTL-level circuits; contribute to system- and chip-level architecture and floorplanning.
• Optimize hardware for performance, power, and cost and evaluate feasibility of complex algorithms.
• Write and maintain scripts and automation for verification flows (Python/Perl/Bash) and work in a Linux environment.
• Comply with security requirements; selected applicants must obtain and maintain a government security clearance.

Requirements

Must-have technical skills and experience:

• Fluent in SystemVerilog, including SVA.
• Recent practical experience with UVM/UVMF and coverage-driven verification.
• Familiarity with at least one major industry simulator (QuestaSim, Xcelium, or VCS).
• Experience with common bus protocols (examples: DDR3/DDR4, AMBA AXI).
• Strong understanding of constrained-random testing and functional/code coverage closure techniques.
• Experience using formal analysis tools.
• Scripting ability (Python, Perl, Bash) and comfortable working in Linux.
• Strong verbal and written communication, organization, and problem-solving skills.

Nice-to-have:

• Experience with mixed-signal verification, FPGA flows, or ASIC physical-layout considerations.
• Prior mentoring or code-review experience in verification teams.

Education Requirements

Requires a bachelor’s degree in Engineering or a related field; master’s degree preferred. Relevant fields explicitly referenced include Integrated Circuits, ASIC Hardware Engineering, or related technical engineering disciplines. (Experience guidance: 3–5 years with a bachelor’s degree, or 0–2 years with a master’s degree.)

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.