UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

The UVM Digital Verification Engineer will develop and execute verification strategies for FPGA and ASIC designs across embedded security, cryptography, signal/image processing, navigation, and communications domains. You will work on block- and chip-level verification, author verification plans, implement UVM testbenches, and collaborate with RTL designers to close functional and code coverage.

Experience Level

Mid-level. Typical experience: 3–5 years with a bachelor’s degree, or 0–2 years with a master’s degree in relevant fields.

Responsibilities

Primary responsibilities include planning and implementing verification activities from block to chip level and supporting design teams to resolve functional issues.

• Develop verification approaches and author/execute verification plans.
• Design and implement UVM agents and testbenches (block- and chip-level).
• Instantiate and integrate VIPs for standard buses; validate proprietary bus agents.
• Perform constrained-random testing and coverage-driven verification; implement covergroups and close coverage.
• Use formal analysis tools to supplement simulation-based verification.
• Work with RTL designers to debug and resolve simulation and functional issues.
• Perform code reviews and mentor junior engineers on verification best practices.
• Automate verification flows and regression runs using scripting in a Linux environment.

Requirements

Must-have technical skills, plus preferred/optional items listed separately.

• Must-have: Fluent in SystemVerilog (including SVA) and recent hands-on UVM/UVMF experience.
• Must-have: Experience with at least one major industry simulator (Questasim, Xcelium, VCS).
• Must-have: Strong grasp of constrained-random testing, coverage-driven verification, and experience closing code/functional coverage.
• Must-have: Experience with industry bus standards (examples: DDR3/DDR4, AMBA AXI) and integrating VIPs.
• Must-have: Experience with formal analysis and familiarity with scripting (Python, Perl, Bash) for automation in Linux.
• Must-have: Strong analytical, communication, organization, and time-management skills.
• Must-have: Applicants selected will be required to obtain and maintain a government security clearance.
• Nice-to-have: Background in embedded security, cryptography, signal/image processing, navigation, or communications.

Education Requirements

Bachelor's degree in Engineering or a related field is required; Master’s degree preferred. Relevant fields noted include Integrated Circuits, ASIC Hardware Engineering, or closely related technical disciplines; equivalent practical experience may be considered per the posting.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.