UVM Digital Verification Engineer
Member of Draper's Digital Design Team responsible for planning and executing verification for FPGA and ASIC designs across domains such as embedded security, cryptography, signal and image processing, navigation, and communications.
Deliver verification strategies, develop UVM testbenches and agents, and work with multi-disciplinary teams to close functional and code coverage on complex designs.
Mid-level — typically 3–5 years of industry experience with a bachelor's degree, or 0–2 years with a master's degree. Recent hands-on UVM/SystemVerilog verification experience is expected.
Primary responsibilities include verification planning, implementation, and collaboration with RTL and system teams.
Must-have technical skills and experience.
Requires a bachelor's degree in Engineering or a related field; a master's degree is preferred. Relevant study areas include Integrated Circuits, ASIC Hardware Engineering, or related electrical/computer engineering fields. The posting allows 3–5 years' experience with a bachelor's or 0–2 years with a master's as alternative experience routes.
Company: Draper
Headquarters: Cambridge, MA, United States
Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.
