UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

Join Draper's Digital Design Team to develop and execute verification strategies for complex digital and mixed-signal FPGA and ASIC designs in embedded security, cryptography, signal/image processing, navigation, and communications.

You will author verification plans, build UVM testbenches and agents, use formal tools, collaborate with RTL designers, and contribute to system- and chip-level verification efforts.

Experience Level

Mid-level. Typical experience: 3–5 years with a Bachelor's degree, or 0–2 years with a Master's degree in Integrated Circuits / ASIC Hardware Engineering or a related area.

Responsibilities

Primary responsibilities include verification development and collaboration with digital design teams.

• Develop verification approaches and author/execute verification plans.
• Design and implement UVM agents and testbenches at block and chip level.
• Instantiate and integrate VIP for industry-standard buses.
• Work with RTL designers to debug simulation issues and close functional coverage.
• Implement cover groups and drive coverage closure to target levels.
• Use formal analysis tools to complement simulation-based verification.
• Perform code reviews and mentor junior engineers.
• Contribute to system-level design reviews and hardware feasibility evaluations.
• Participate in floor-planning/physical verification activities when needed.

Requirements

Must-have technical skills, tools, and qualifications.

• Fluency in SystemVerilog, including SystemVerilog Assertions (SVA).
• Recent experience with UVM or UVMF and constrained-random, coverage-driven methodologies.
• Experience with at least one major industry simulator (QuestaSim, Xcelium, VCS).
• Familiarity with at least one IEEE/industry bus standard; experience with DDR3/DDR4 and AMBA AXI is preferred.
• Experience with formal verification tools and methods.
• Scripting skills (Python, Perl, Bash or similar) and ability to work in a Linux environment.
• Strong analytical, written and verbal communication skills; ability to prioritize tasks and meet deadlines.
• Ability to obtain and maintain a U.S. government security clearance (required for selected applicants).

Education Requirements

Requires a Bachelor's degree in Engineering or a related field; a Master's degree is preferred. The posting specifies experience expectations tied to degree level: 3–5 years of experience with a Bachelor's, or 0–2 years with a Master's. No alternative "equivalent experience" language was provided.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.