UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

Develop and execute verification strategies and testbenches for FPGA and ASIC digital designs using UVM and SystemVerilog. Work on designs in embedded security, cryptography, signal and image processing, navigation, and communications within a multidisciplinary digital design team.

Collaborate with RTL designers, formal analysts, and system engineers to close functional coverage, resolve simulation issues, and verify block- and chip-level behavior.

Experience Level

Mid-level — typically 3–5 years of relevant experience with a bachelor's degree, or 0–2 years with a master's degree.

Responsibilities

Primary verification and collaboration duties:

• Develop verification approaches and author/execute verification plans for block- and chip-level designs.
• Design and implement UVM agents, testbenches, and verification components; instantiate VIP for standard buses.
• Create and maintain SVA assertions and cover groups; drive code and functional coverage closures toward targets.
• Use formal analysis tools and constrained-random testing to validate design correctness.
• Run simulations on major industry simulators and debug/resolve issues with RTL designers.
• Perform code reviews, document verification results, and mentor junior engineers.
• Script automation and data analysis in Python, Perl, Bash, or similar; operate in a Linux environment.
• Contribute to system-level design evaluation and collaborate on hardware feasibility and tradeoffs.
• Obtain and maintain required government security clearance as a condition of employment.

Requirements

Must-have technical skills and experience:

• Fluent in SystemVerilog, including SVA; recent practical experience with UVM/UVMF.
• Experience with at least one major simulator (QuestaSim, Xcelium, VCS).
• Familiarity with common IEEE bus standards and protocols (examples: DDR3/DDR4, AMBA/AXI).
• Strong understanding of constrained-random testing and coverage-driven verification methodologies.
• Practical experience with formal analysis tools and methodologies.
• Proficiency with scripting for automation (Python, Perl, Bash) and working in Linux.
• Strong verbal and written communication, organization, and problem-solving skills.
• Ability to work in multidisciplinary teams and mentor junior staff.
• Ability to obtain and maintain a government security clearance.

Education Requirements

Bachelor's degree in Engineering or a related field required; Master's degree preferred. Relevant fields include Integrated Circuits, ASIC Hardware Engineering, or related technical disciplines. Experience guidance: typically 3–5 years with a bachelor's degree, or 0–2 years with a master's degree.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.