UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

The UVM Digital Verification Engineer will develop and execute verification strategies for digital and mixed-signal FPGA and ASIC designs across domains such as embedded security, cryptography, signal and image processing, navigation, and communications.

You will work on multi-disciplinary teams to create verification plans, develop UVM testbenches and agents, perform coverage-driven verification and formal analysis, and collaborate with RTL designers to close functional and code coverage.

Experience Level

Mid-level. Typical experience expectation: 3–5 years with a bachelor’s degree, or 0–2 years with a master’s degree.

Responsibilities

Core responsibilities include verification planning, testbench and tool use; additional hardware design tasks are possible depending on project needs.

• Develop verification approaches and author/execute verification plans and test cases.
• Implement UVM agents, instantiate VIP for standard buses, and build block- and chip-level UVM testbenches.
• Write SystemVerilog (including SVA) testbenches and use constrained-random testing and coverage-driven methodologies to achieve coverage goals.
• Implement cover groups, close functional and code coverage, and perform code reviews; mentor junior engineers.
• Use formal analysis tools to augment simulation-based verification.
• Work with RTL designers to diagnose and resolve simulation issues and verify fixes.
• Use scripting (Python, Perl, Bash) and work in a Linux environment to automate verification and regression flows.
• Support system-level design evaluation and, when required, contribute to hardware feasibility assessments and transistor-level simulation activities.

Requirements

Technical must-haves and required clearances.

• Fluent in SystemVerilog, including SVA.
• Recent hands-on experience with UVM/UVMF and constrained-random, coverage-driven verification.
• Experience with at least one major simulator (e.g., Questasim, Xcelium, VCS).
• Familiarity with common bus/protocols (examples: DDR3/DDR4, AMBA AXI).
• Experience with formal verification tools and methodologies.
• Proficiency with scripting (Python, Perl, Bash) and working in Linux.
• Strong analytical, communication, and time-management skills; ability to mentor others.
• Ability to obtain and maintain a U.S. government security clearance is required.

Education Requirements

Requires a bachelor’s degree in Engineering or a related field. Master’s degree preferred. Typical experience mapping provided in the posting: 3–5 years of relevant experience with a bachelor’s degree, or 0–2 years with a master’s degree. Fields referenced include Integrated Circuits, ASIC Hardware Engineering, or related technical disciplines. Equivalent practical experience implied by the experience/degree matrix.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.