Host and Network IO FPGA Engineer

Job Title

Host and Network IO FPGA Engineer

Role Summary

The Host and Network IO FPGA Engineer designs and implements FPGA-based IO subsystems connecting server clusters to Cerebras wafer-scale engines. The role spans chassis-to-wafer IO architecture, FPGA RTL development, production bitstream delivery, and cross-team integration with board, software, and cluster teams.

Work focuses on optimizing bandwidth, latency, and reliability across RoCE/RDMA interfaces, switching fabrics, and serial links to the wafer-scale engine.

Experience Level

Mid-level. Typical candidates have significant production FPGA experience (guidance in posting: 5+ years industry FPGA development; alternatives summarized under Education Requirements).

Responsibilities

Key responsibilities include:

• Architect and design chassis-to-wafer IO subsystems, including RoCE v2 RDMA interfaces, programmable switching fabric, and serial IO to the WSE.
• Develop and improve FPGA RTL (Verilog), produce production-ready bitstreams, and iterate across hardware generations.
• Optimize datapaths for bandwidth, latency, congestion control, and fairness.
• Collaborate with DV, embedded software, board, and cluster teams to prevent defects, simplify debug, and execute board bring-up.
• Drive network performance debugging in large AI clusters and integrate networking protocols and technologies.
• Lead cross-functional technical projects and communicate effectively with stakeholders.

Requirements

Must-have technical skills and experience:

• Extensive experience delivering production FPGA solutions: Verilog RTL development in Git-based workflows.
• Strong FPGA toolchain proficiency: placement & routing, timing closure, simulation, and hardware debug workflows.
• Experience with network protocols and debugging (TCP, RoCE) and tools such as Wireshark.
• Familiarity with network switch environments or willingness to learn commercial switch platforms (e.g., Arista, Juniper).
• Proven ability to produce deployment-ready bitstreams and to support large-cluster deployments.
• Ability to lead technical projects and coordinate across hardware and software teams.

Nice-to-have:

• Experience with RDMA, custom network stacks, or large-scale AI cluster networking.
• Background in high-performance serial protocols and custom on-chip/off-chip interfaces.

Education Requirements

Posting specifies either: 5+ years industry experience generating production FPGA solutions; OR a Master’s or PhD in Computer or Electrical Engineering plus 3 years industry experience. Equivalent practical industry experience is presented as an alternative to the academic path.

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.