UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

Member of Draper’s Digital Design Team responsible for developing and executing verification strategies for FPGA and ASIC designs. Work spans digital and mixed-signal systems in embedded security, cryptography, signal/image processing, navigation, and communications.

Experience Level

Mid-level. Typical experience: 3–5 years with a bachelor’s degree or 0–2 years with a master’s degree in Integrated Circuits/ASIC hardware or a related field.

Responsibilities

Primary verification and engineering tasks for block- and chip-level digital designs.

• Develop verification approaches and author/execute verification plans.
• Implement UVM testbenches and develop UVM agents for proprietary buses.
• Instantiate VIPs for industry-standard buses and work in block-level and chip-level UVM environments.
• Perform constrained-random testing, coverage-driven verification, and implement covergroups per requirements.
• Use formal analysis tools and drive code and functional coverage closures.
• Collaborate with RTL designers to resolve simulation issues and perform code reviews; mentor junior engineers.
• Automate verification activities using scripting and run simulations on industry simulators.
• Contribute to system-level design discussions and evaluate hardware feasibility of algorithms.

Requirements

Must-have technical skills, tools, and clearances.

• Fluent in SystemVerilog, including SVA; recent experience with UVM/UVMF.
• Experience with at least one major industry simulator (QuestaSim, Xcelium, VCS).
• Familiarity with IEEE/industry bus standards and protocols (examples: DDR3/DDR4, AMBA AXI).
• Strong understanding of constrained-random testing and coverage-driven verification.
• Experience with formal analysis tools and verification methodologies.
• Proficiency in scripting (Python, Perl, Bash) and working in a Linux environment.
• Strong analytical, communication, and time-management skills; ability to prioritize tasks.
• Eligible to obtain and maintain a U.S. government security clearance.
• Experience guidance: 3–5 years with a bachelor’s degree, or 0–2 years with a master's degree.

Nice-to-have:

• Experience with FPGA and ASIC flows, VIP development, or transistor-level simulation and layout exposure.
• Background in embedded security, cryptography, or signal/image processing applications.

Education Requirements

Requires a bachelor’s degree in Engineering or a related field; a master’s degree is preferred. Typical fields include Integrated Circuits, ASIC Hardware Engineering, Electrical/Computer Engineering, Computer Science, or related technical disciplines. Equivalent practical experience may be considered.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.