Staff Design Verification Engineer – Cache Verification

Job Title

Staff Design Verification Engineer – Cache Verification

Role Summary

Drive verification of L2/L3 cache and memory-subsystem functionality with emphasis on coherency, ordering, correctness, and subsystem integration. Individual-contributor role responsible for verification planning, environment development, debug, and improving team verification methodology.

Experience Level

Senior — requires 7+ years of ASIC/CPU/SoC design verification experience.

Responsibilities

Accountable for verification planning through subsystem signoff and for building robust, reusable verification infrastructure.

• Plan and execute verification for L2/L3 caches and related cache-subsystem features from block-level to subsystem integration.
• Develop and maintain SystemVerilog/UVM environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Define and run directed and constrained-random tests to surface corner cases in coherency, concurrency, backpressure, and error scenarios.
• Analyze failures, isolate root causes, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate with architecture, design, and verification teams to clarify requirements and improve verification early in the cycle.
• Write functional coverage, analyze results, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable methodology, automation, and debug improvements to raise team productivity and verification quality.

Requirements

Must-have skills and experience. Preferred items listed as Nice-to-have.

• Must-have: 7+ years of ASIC, CPU, or SoC design verification with ownership of complex block or subsystem verification.
• Must-have: Strong SystemVerilog and UVM-based verification expertise.
• Must-have: Strong understanding of cache architecture, memory hierarchy, and cache coherency protocols/behavior.
• Must-have: Experience building reusable testbenches, assertions, checkers, scoreboards, coverage models, and debug infrastructure.
• Must-have: Strong debugging and root-cause analysis across specification, RTL, and testbench layers.
• Must-have: Experience with coverage analysis and closure, constrained-random verification, and metrics-driven signoff.
• Nice-to-have: Experience verifying multiple cache levels, memory consistency, weak ordering, multicore verification, performance-oriented verification, formal techniques, or emulation/FPGA-assisted debug.
• Nice-to-have: Familiarity with Python, C/C++, or scripting languages used for DV infrastructure and automation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.